{"157651":{"#nid":"157651","#data":{"type":"event","title":"Nano@Tech Seminar Series","body":[{"value":"\u003Cp align=\u0022center\u0022\u003E\u003Cstrong\u003EFriday, October 12\u003Csup\u003Eth\u003C\/sup\u003E\u003C\/strong\u003E\u003Cstrong\u003E at 12 noon\u003C\/strong\u003E\u003C\/p\u003E\u003Cp align=\u0022center\u0022\u003EMarcus Nanotechnology Building Conference Room\u003C\/p\u003E\u003Cp align=\u0022center\u0022\u003E\u0026nbsp;\u003Cstrong\u003E\u003Cstrong\u003ETopic:\u003C\/strong\u003E\u0026nbsp; High Volume Manufacturing Challenges at Intel\u003C\/strong\u003E\u003C\/p\u003E\u003Cp align=\u0022center\u0022\u003E\u003Cstrong\u003EDr. Ivan Murzin\u003C\/strong\u003E\u003C\/p\u003E\u003Cp align=\u0022center\u0022\u003EStaff Process Engineer\u003C\/p\u003E\u003Cp align=\u0022center\u0022\u003EIntel Corp.\u003C\/p\u003E\u003Cp\u003EMoore\u0027s law is the observation that over the \u003Ca title=\u0022:http:\/\/en.wikipedia.org\/wiki\/History_of_computing_hardware\nHistory of computing hardware\u0022 href=\u0022http:\/\/en.wikipedia.org\/wiki\/History_of_computing_hardware\u0022\u003Ehistory of computing hardware\u003C\/a\u003E the number of \u003Ca title=\u0022:http:\/\/en.wikipedia.org\/wiki\/Transistor\nTransistor\u0022 href=\u0022http:\/\/en.wikipedia.org\/wiki\/Transistor\u0022\u003Etransistors\u003C\/a\u003E on \u003Ca title=\u0022:http:\/\/en.wikipedia.org\/wiki\/Integrated_circuit\nIntegrated circuit\u0022 href=\u0022http:\/\/en.wikipedia.org\/wiki\/Integrated_circuit\u0022\u003Eintegrated circuits\u003C\/a\u003E doubles approximately every two years. For the past 45 years, relentless focus on Moore\u2019s Law transistor scaling has provided ever-increasing Complementary Metal\u2013Oxide\u2013Semiconductor (CMOS) transistor performance and density. For much of this time, Moore\u2019s Law transistor scaling meant \u201cclassic\u201d Dennard scaling. However, in recent years, Dennard scaling has become less influential. More specifically, for generations after the 130 nm node (90 nm, 65 nm, 45 nm, 32 nm, 22 nm) performance enhancers (such as SiGe induced strain and high-k metal gate) have been added to continue to drive the transistor roadmap forward. In this talk, scaling transistor innovation will be overviewed as a part of the pursuit of power constraint, standby power dominated devices.\u0026nbsp; Scaling imposes great challenges on the processing technology involved in semiconductor manufacturing as well as drives the need to pursue advanced materials.\u0026nbsp; We will highlight the examples of such challenges in development of low-k advanced dielectrics and thin film deposition methods (atomic layer deposition) as well the ways of overcoming these. \u003C\/p\u003E\u003Cp\u003E\u003Cem\u003E\u003Cstrong\u003ESpeaker:\u0026nbsp;\u003C\/strong\u003E Dr. Ivan Murzin is a Staff Process Engineer in F17 P840 Program in Technology and Manufacturing Division at Intel. He has 20+ years of experience in Thin Films (both PVD and CVD), ion beam surface modification and Material Analysis. Ivan has a PhD in Material Science (1992) and holds the certificate in Management from Harvard University Extension School (2007). Ivan has more than 30 papers published in the international journals and conferences and holds 5 US patents. Ivan authored 50+ white papers on process and equipment improvements while being the process engineer at Intel. In 2011, Dr. Murzin received the \u201cExcellence of a Faculty as an Educator and Faculty Advisor Award\u201d category for the FSM \u201cExcellence in Technical Leadership Advancement through Education\u201d Annual Award for College of Engineering.\u0026nbsp; In 2012 he became Adjunct Professor at Georgia Tech via the Intel College of Engineering program. In addition to thin film deposition processes, Dr. Murzin\u0027s current professional interests include magnetic, chemical, electrical and mechanical properties of material interfaces.\u003C\/em\u003E \u003C\/p\u003E\u003Cp align=\u0022center\u0022\u003E\u003Cstrong\u003E\u003Cem\u003EPizza lunch is provided, however we ask that you limit yourself to two slices so as many attendees as possible can be accommodated.\u003C\/em\u003E\u003C\/strong\u003E\u003C\/p\u003E","summary":null,"format":"limited_html"}],"field_subtitle":"","field_summary":[{"value":"\u003Cp\u003ENano@Tech\u003C\/p\u003E","format":"limited_html"}],"field_summary_sentence":"","uid":"27716","created_gmt":"2012-09-28 08:36:15","changed_gmt":"2016-10-08 02:00:10","author":"Shanda Jones-Blair","boilerplate_text":"","field_publication":"","field_article_url":"","field_event_time":{"event_time_start":"2012-10-12T13:00:00-04:00","event_time_end":"2012-10-12T14:00:00-04:00","event_time_end_last":"2012-10-12T14:00:00-04:00","gmt_time_start":"2012-10-12 17:00:00","gmt_time_end":"2012-10-12 18:00:00","gmt_time_end_last":"2012-10-12 18:00:00","rrule":null,"timezone":"America\/New_York"},"extras":["free_food"],"groups":[{"id":"1271","name":"NanoTECH"}],"categories":[],"keywords":[{"id":"4315","name":"nano@tech"}],"core_research_areas":[],"news_room_topics":[],"event_categories":[{"id":"1795","name":"Seminar\/Lecture\/Colloquium"}],"invited_audience":[],"affiliations":[],"classification":[],"areas_of_expertise":[],"news_and_recent_appearances":[],"phone":[],"contact":[{"value":"\u003Cp\u003EDavid Gottfried - \u003Ca href=\u0022mailto:dsgottfried@gatech.edu\u0022\u003Edsgottfried@gatech.edu\u003C\/a\u003E\u003C\/p\u003E","format":"limited_html"}],"email":[],"slides":[],"orientation":[],"userdata":""}}}