{"301321":{"#nid":"301321","#data":{"type":"news","title":"Georgia Tech Teams with Intel, SRC to Advance Spintronics","body":[{"value":"\u003Cp\u003EGeorgia Institute of Technology researchers collaborating with and sponsored by Intel Corporation through the Semiconductor Research Corporation (SRC), the world\u2019s leading university-research consortium for semiconductors and related technologies, have developed a physics-based modeling platform that advances spintronics interconnect research for beyond-CMOS computing.\u003C\/p\u003E\u003Cp\u003ESpin-logic aims at reducing power consumption of electronic devices, thereby improving battery life and reducing energy consumption in computing for a whole range of electronic product applications from portable devices to data centers.\u003C\/p\u003E\u003Cp\u003E\u201cAfter more than four decades of exponential growth in the performance of electronic integrated circuits, it is now apparent that improving the energy efficiency of computing is a primary challenge,\u201d said Ian A. Young, a collaborator and co-author of the research and a Senior Fellow at Intel Corporation. \u201cThere is a global search for information processing elements that use computational state variables other than electronic charge, and these devices are being sought to bring in new functionalities and further lower the power dissipation in computers.\u201d\u003C\/p\u003E\u003Cp\u003EOne of the main motivations behind the search for a next-generation computing switch beyond CMOS (complementary metal oxide semiconductor) devices is to sustain the advancement of Moore\u2019s Law. Nanomagnetic\/spintronic devices provide a complementary option to electronics. The added functionality of this option includes the non-volatility of information on-chip, which is in essence a combination of logic and memory functions. However, to benefit from the increase in density of the on-chip devices, there has to be adequate connectivity among the switches\u2014which is the focus of the Georgia Tech research effort spearheaded by Azad Naeemi, an associate professor in the School of Electrical and Computer Engineering (ECE).\u003C\/p\u003E\u003Cp\u003EAmong the potential alternatives, devices based on nanoscale magnets in the field of spintronics have received special attention thanks to their advantages in terms of robustness and enhanced functionality. Magnets are non-volatile: their state remains even if the power to the circuit is switched off. Thus, the circuits do not consume power when not used\u2014a very desirable property for modern tablets and smart phones.\u003C\/p\u003E\u003Cp\u003EOne of the most important aspects of any new information processing element is how fast and power efficient they can communicate over an interconnect system with one another. In today\u2019s CMOS chips, more energy is consumed communicating between transistor logic functions than actually processing of information. The Georgia Tech research has therefore focused on this important aspect of communicating between spin-logic devices and demonstrates that interconnects are an even more important challenge for beyond-CMOS switches.\u003C\/p\u003E\u003Cp\u003ETo analyze spintronic interconnects, the Georgia Tech team and their Intel collaborators have developed compact models for spin transport in copper and aluminum\u2014taking into account the scattering at wire surfaces and grain boundaries that become quite dominant at nanoscale dimensions. The research team has also developed compact models for the nanomagnet dynamic, electronic and spintronic transport through magnet to non-magnet interfaces, electric currents and spin diffusion. These models are all based on familiar electrical elements such as resistors and capacitors and can therefore be analyzed using standard circuit simulation tools such as SPICE.\u003C\/p\u003E\u003Cp\u003E\u201cThis work is showing the way for how spintronics can create energy-efficient computation by including not only the spin logic functional circuit blocks, but also the interconnect system parameters,\u201d said Jon Candelaria, director of Interconnect and Packaging Sciences at SRC. \u201dThis will help establish a much more realistic and accurate prediction of computing performance and power with spintronics.\u201d\u003C\/p\u003E\u003Cp\u003EThe research paper was presented at the IEEE International Interconnect Technology Conference on May 24 in San Jose, Calif., (\u003Ca href=\u0022http:\/\/www.iitc-conference.org\/novel-systems-ii.html\u0022\u003Ehttp:\/\/www.iitc-conference.org\/novel-systems-ii.html\u003C\/a\u003E). The co-authors are Rouhollah Mousavi Iraei and Nickvash Kani, both Georgia Tech ECE Ph.D. students; Phillip Bonhomme, an M.S.E.C.E. graduate of Georgia Tech who now works at Intel; Sasikanth Manipatruni, Dmitri E. Nikonov, and Ian A. Young, all of Intel; and Naeemi.\u003C\/p\u003E","summary":null,"format":"limited_html"}],"field_subtitle":[{"value":"New Findings to Help Reduce Power Consumption of Electronic Devices, Improve Battery Life"}],"field_summary":[{"value":"\u003Cp\u003EGeorgia Tech researchers collaborating with and sponsored by Intel Corporation through the Semiconductor Research Corporation (SRC), the world\u2019s leading university-research consortium for semiconductors and related technologies, have developed a physics-based modeling platform that advances spintronics interconnect research for beyond-CMOS computing.\u003C\/p\u003E","format":"limited_html"}],"field_summary_sentence":[{"value":"Georgia Tech researchers, collaborating with and sponsored by Intel Corporation through the Semiconductor Research Corporation, have developed a physics-based modeling platform that advances spintronics interconnect research for beyond-CMOS computing"}],"uid":"27241","created_gmt":"2014-06-04 14:21:07","changed_gmt":"2016-10-08 03:16:33","author":"Jackie Nemeth","boilerplate_text":"","field_publication":"","field_article_url":"","dateline":{"date":"2014-06-04T00:00:00-04:00","iso_date":"2014-06-04T00:00:00-04:00","tz":"America\/New_York"},"extras":[],"related_links":[{"url":"http:\/\/www.gatech.edu\/","title":"Georgia Tech"},{"url":"http:\/\/www.ece.gatech.edu\/","title":"School of Electrical and Computer Engineering"},{"url":"http:\/\/www.ece.gatech.edu\/faculty-staff\/fac_profiles\/bio.php?id=159","title":"Azad Naeemi"},{"url":"https:\/\/www.src.org\/","title":"Semiconductor Research Corporation"},{"url":"http:\/\/intel.com\/","title":"Intel"}],"groups":[{"id":"1255","name":"School of Electrical and Computer Engineering"}],"categories":[{"id":"134","name":"Student and Faculty"},{"id":"153","name":"Computer Science\/Information Technology and Security"},{"id":"144","name":"Energy"},{"id":"145","name":"Engineering"},{"id":"149","name":"Nanotechnology and Nanoscience"},{"id":"135","name":"Research"},{"id":"150","name":"Physics and Physical Sciences"}],"keywords":[{"id":"5518","name":"Azad Naeemi"},{"id":"109","name":"Georgia Tech"},{"id":"94731","name":"Intel Corporation"},{"id":"166855","name":"School of Electrical and Computer Engineering"},{"id":"166953","name":"Semiconductor Research Corporation"}],"core_research_areas":[{"id":"39451","name":"Electronics and Nanotechnology"},{"id":"39531","name":"Energy and Sustainable Infrastructure"}],"news_room_topics":[],"event_categories":[],"invited_audience":[],"affiliations":[],"classification":[],"areas_of_expertise":[],"news_and_recent_appearances":[],"phone":[],"contact":[{"value":"\u003Cp\u003EDan Francisco\u003C\/p\u003E\u003Cp\u003EIntegrity Global for SRC\u003C\/p\u003E\u003Cp\u003E916-812-8814\u003C\/p\u003E","format":"limited_html"}],"email":["dan@integrityglobal.biz"],"slides":[],"orientation":[],"userdata":""}}}