The title of the award-winning paper is “System-level variation-aware aging simulator using a unified novel gate-delay model for bias temperature instability, hot carrier injection, and gate oxide breakdown,” and it was published in Microelectronics and Reliability, vol. 55, nos. 9-10, pp. 1334-1340, August-September 2015.

The paper presents software that has been developed to estimate the lifetime of logic circuits due to a variety of front-end-of-line (FEOL) wearout mechanisms. It takes into account operating temperatures, IR drops, and stress probabilities while running benchmarks. It also takes into account system performance requirements, several FEOL wearout mechanisms (gate oxide breakdown, hot carrier injection, bias temperature instability), and a wide variety of use scenarios. Statistical analysis identifies critical paths and provides accurate estimates of the distribution of lifetimes under process, supply voltage, temperature, and aging variations. The software enables the replacement of arbitrary timing guardbands for aging with guardbands based on process data and system usage.