EPS Distinguished Lecturers are selected from among EPS Fellows, award winners, and society leaders. Selected experts are highly regarded members of the technical community and renowned experts in their respective fields. They are invited to deliver lectures and courses at EPS events, including chapters, conferences, workshops, symposia, and IEEE Student Chapter events.

Notably, Tentzeris has previously served as a Distinguished Lecturer for the IEEE Microwave Theory and Technology Society (MTT) and the IEEE Council on Radio Frequency Identification (CRFID), highlighting his exceptional contributions across multiple societies within IEEE (Institute of Electrical and Electronics Engineers).

Since 2016, Tentzeris has held the Ken Byers Professorship in flexible electronics in ECE. He joined the faculty in 1998 and leads the ATHENA Research Group. Tentzeris’ research specializes in 3D Printed RF electronics, antennas and modules, flexible and conformal electronics and phased antenna arrays up to sub-THz, origami and morphing electromagnetics, Highly Integrated/Multilayer Packaging for RF and Wireless Applications using ceramic and organic flexible materials, “green” paper-based RFIDs and sensors, nanostructures for RF, wireless sensors, energy harvesting and wireless power transfer/wireless power grids, reconfigurable intelligent metasurfaces, heterogeneous integration and SOP-integrated (UWB, multiband, conformal) antennas.

As an EPS Distinguished Lecturer, Tentzeris will deliver lectures on Smart Cities, Smart Agriculture, Smart Manufacturing/Industry 4.0, and Digital Twin domains.

Corrective solutions to the issue of MAs have, thus far, been either expensive to implement, such as filtering software, or cause discomfort to the wearer, such as tighter strap attachments and stronger, skin irritating adhesives. The team of W. Hong Yeo, Associate Professor in the George W. Woodruff School of Mechanical Engineering & PI of the Yeo Group & Director of Center for HCIE, working with partners at the Korea Advanced Institute of Science and Technology and Emory University have designed a flexibly packaged wireless wearable ECG device using a new class of strain-isolating materials that reduces MAs, induced by movement in the skin/sensor contact area.

The team’s new strain-isolated, wearable soft bioelectronic system (SIS) adheres naturally to the skin using a breathable soft membrane for continuous conformal contact. A pair of nanomembrane mesh electrodes and a thin-film circuit powered by rechargeable lithium-ion batteries are placed on a thin layer of silicone gel to allow a greater range of motion and packaged within a low modulus silicone elastomer. In testing the design against commercially available skin-mounted biosensors, the team’s new device provides real-time wireless data of multiple physiological signals with a significant reduction in MA interference. Additionally, and most importantly, the device trial participants exhibited no device lamination issues, excessive sweating, signal degradation, or increased skin irritation.

Yeo and his team are pleased with their results to-date but have plans to take the research even further. The team seeks an even smaller device footprint by integrating fan-out wafer-level packaging and developing all-printing fabrication methods. Additionally, the team is planning large-scale clinical studies in cardiology and pediatrics to monitor the health status of both inpatient and outpatient groups on a continuous basis.

- Christa M. Ernst

Rodeheaver, N., Herbert, R., Kim, Y.-S., Mahmood, M., Kim, H., Jeong, J.-W., Yeo, W.-H., Strain-Isolating Materials and Interfacial Physics for Soft Wearable Bioelectronics and Wireless, Motion Artifact-Controlled Health Monitoring. Adv. Funct. Mater. 2021, 2104070. https://doi.org/10.1002/adfm.202104070
 

Media Relations Contact: Christa Ernst (christa.ernst@research.gatech.edu)

Flow of lithium ions into and out of alloy battery anodes has long been a limiting factor in how much energy batteries could hold using conventional materials. Too much ion flow causes anode materials to swell and then shrink during charge-discharge cycles, causing mechanical degradation that shortens battery life. To address that issue, researchers have previously developed hollow “yolk-shell” nanoparticles that accommodate the volume change caused by ion flow, but fabricating them has been complex and costly.

Now, a research team has discovered that particles a thousand times smaller than the width of a human hair spontaneously form hollow structures during the charge-discharge cycle without changing size, allowing more ion flow without damaging the anodes. The research was reported June 1 in the journal Nature Nanotechnology.

“Intentionally engineering hollow nanomaterials has been done for a while now, and it is a promising approach for improving the lifetime and stability of batteries with high energy density,” said Matthew McDowell, assistant professor in the George W. Woodruff School of Mechanical Engineering and the School of Materials Science and Engineering at the Georgia Institute of Technology. “The problem has been that directly synthesizing these hollow nanostructures at the large scales needed for commercial applications is challenging and expensive. Our discovery could offer an easier, streamlined process that could lead to improved performance in a way that is similar to the intentionally engineered hollow structures.”

The researchers made their discovery using a high-resolution electron microscope that allowed them to directly visualize battery reactions as they occur at the nanoscale. “This is a tricky type of experiment, but if you are patient and do the experiments right, you can learn really important things about how the materials behave in batteries,” McDowell said.

The team, which included researchers from ETH Zürich and Oak Ridge National Laboratory, also used modeling to create a theoretical framework for understanding why the nanoparticles spontaneously hollow — instead of shrinking — during removal of lithium from the battery.

The ability to form and reversibly fill hollow particles during battery cycling occurs only in oxide-coated antimony nanocrystals that are less than approximately 30 nanometers in diameter. The research team found that the behavior arises from a resilient native oxide layer that allows for initial expansion during lithiation — flow of ions into the anode — but mechanically prevents shrinkage as antimony forms voids during the removal of ions, a process known as delithiation.

The finding was a bit of a surprise because earlier work on related materials had been performed on larger particles, which expand and shrink instead of forming hollow structures. “When we first observed the distinctive hollowing behavior, it was very exciting and we immediately knew this could have important implications for battery performance,” McDowell said.

Antimony is relatively expensive and not currently used in commercial battery electrodes. But McDowell believes the spontaneous hollowing may also occur in less costly related materials such as tin. Next steps would include testing other materials and mapping a pathway to commercial scale-up.

“It would be interesting to test other materials to see if they transform according to a similar hollowing mechanism,” he said. “This could expand the range of materials available for use in batteries. The small test batteries we fabricated showed promising charge-discharge performance, so we would like to evaluate the materials in larger batteries.”

Though they may be costly, the self-hollowing antimony nanocrystals have another interesting property: they could also be used in sodium-ion and potassium-ion batteries, emerging systems for which much more research must be done.

“This work advances our understanding of how this type of material evolves inside batteries,” McDowell said. “This information will be critical for implementing the material or related materials in the next generation of lithium-ion batteries, which will be able to store more energy and be just as durable as the batteries we have today.”

In addition to McDowell, the paper’s authors include Matthew Boebinger from Georgia Tech; Olesya Yarema, Maksym Yarema, and Vanessa Wood from the Department of Information Technology and Electrical Engineering at ETH Zürich , and Kinga Unocic and Raymond Unocic from the Center for Nanophase Materials Science at Oak Ridge National Laboratory.

This work was performed at the Georgia Tech Materials Characterization Facility and the Institute for Electronics and Nanotechnology, a member of the National Nanotechnology Coordinated Infrastructure, which is supported by the National Science Foundation (Grant ECCS-1542174). Support also came from the Department of Energy Office of Science Graduate Student Research Program for research performed at Oak Ridge National Laboratory. A portion of this research was conducted at the Center for Nanophase Materials Sciences, which is a DOE Office of Science User Facility. Support was also provided by a Sloan Research Fellowship in Chemistry from the Alfred P. Sloan Foundation and by the Swiss National Science foundation via an Ambizione Fellowship (no. 161249). The content is solely the responsibility of the authors and does not necessarily represent the official views of the sponsoring organizations.

CITATION: Matthew G. Boebinger, et al., “Spontaneous and reversible hollowing of alloy anode nanocrystals for stable battery cycling” (Nature Nanotechnology, 2020). https://doi.org/10.1038/s41565-020-0690-9

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Media Relations Contact: John Toon (404-894-6986) (jtoon@gatech.edu).

Writer: John Toon

Ravichandran received the award for his paper entitled “Design and Demonstration of 3D Glass Panel Embedded (GPE) Packages for Heterogeneous Integration.” The paper addresses the limitations of current mold-based wafer-level fanout packaging technology by presenting a novel 3D glass-based panel embedded packaging technology to meet the bandwidth, power-efficiency, cost, and reliability requirements of future mobile and high-performance computing applications.

This research was supported by the Industry Consortium at the 3D Systems Packaging Research Center (PRC) at Georgia Tech. Ravichandran, along with his colleagues in the PRC, are developing all of the basic technologies to design and demonstrate 3D GPE packages for a variety of heterogeneous integration applications that include ultra-high bandwidth computing; 5G and millimeter wave communications; MEMS & sensors; IoTs; and flexible, wearable, and low and high-power electronics.

The new structure gives thin-film transistors stability comparable to those made with inorganic materials, allowing them to operate in ambient conditions – even underwater. Organic thin-film transistors can be made inexpensively at low temperature on a variety of flexible substrates using techniques such as inkjet printing, potentially opening new applications that take advantage of simple, additive fabrication processes.

“We have now proven a geometry that yields lifetime performance that for the first time establish that organic circuits can be as stable as devices produced with conventional inorganic technologies,” said Bernard Kippelen, the Joseph M. Pettit professor in Georgia Tech’s School of Electrical and Computer Engineering (ECE) and director of Georgia Tech’s Center for Organic Photonics and Electronics (COPE). “This could be the tipping point for organic thin-film transistors, addressing long-standing concerns about the stability of organic-based printable devices.” 

The research was reported January 12 in the journal Science Advances. The research is the culmination of 15 years of development within COPE and was supported by sponsors including the Office of Naval Research, the Air Force Office of Scientific Research, and the National Nuclear Security Administration.

Transistors comprise three electrodes. The source and drain electrodes pass current to create the “on” state, but only when a voltage is applied to the gate electrode, which is separated from the organic semiconductor material by a thin dielectric layer. A unique aspect of the architecture developed at Georgia Tech is that this dielectric layer uses two components, a fluoropolymer and a metal-oxide layer. 

“When we first developed this architecture, this metal oxide layer was aluminum oxide, which is susceptible to damage from humidity,” said Canek Fuentes-Hernandez, a senior research scientist and coauthor of the paper. “Working in collaboration with Georgia Tech Professor Samuel Graham, we developed complex nanolaminate barriers which could be produced at temperatures below 110 degrees Celsius and that when used as gate dielectric, enabled transistors to sustain being immersed in water near its boiling point.” 

The new Georgia Tech architecture uses alternating layers of aluminum oxide and hafnium oxide – five layers of one, then five layers of the other, repeated 30 times atop the fluoropolymer – to make the dielectric. The oxide layers are produced with atomic layer deposition (ALD). The nanolaminate, which ends up being about 50 nanometers thick, is virtually immune to the effects of humidity.  

“While we knew this architecture yielded good barrier properties, we were blown away by how stably transistors operated with the new architecture,” said Fuentes-Hernandez. “The performance of these transistors remained virtually unchanged even when we operated them for hundreds of hours and at elevated temperatures of 75 degrees Celsius. This was by far the most stable organic-based transistor we had ever fabricated.”

For the laboratory demonstration, the researchers used a glass substrate, but many other flexible materials – including polymers and even paper – could also be used. 

In the lab, the researchers used standard ALD growth techniques to produce the nanolaminate. But newer processes referred to as spatial ALD – utilizing multiple heads with nozzles delivering the precursors – could accelerate production and allow the devices to be scaled up in size. “ALD has now reached a level of maturity at which it has become a scalable industrial process, and we think this will allow a new phase in the development of organic thin-film transistors,” Kippelen said.

An obvious application is for the transistors that control pixels in organic light-emitting displays (OLEDs) used in such devices as the iPhone X and Samsung phones. These pixels are now controlled by transistors fabricated with conventional inorganic semiconductors, but with the additional stability provided by the new nanolaminate, they could perhaps be made with printable organic thin-film transistors instead.

Internet of things (IoT) devices could also benefit from fabrication enabled by the new technology, allowing production with inkjet printers and other low-cost printing and coating processes. The nanolaminate technique could also allow development of inexpensive paper-based devices, such as smart tickets, that would use antennas, displays and memory fabricated on paper through low-cost processes. 

But the most dramatic applications could be in very large flexible displays that could be rolled up when not in use.

“We will get better image quality, larger size and better resolution,” Kippelen said. “As these screens become larger, the rigid form factor of conventional displays will be a limitation. Low processing temperature carbon-based technology will allow the screen to be rolled up, making it easy to carry around and less susceptible to damage. 

For their demonstration, Kippelen’s team – which also includes Xiaojia Jia, Cheng-Yin Wang and Youngrak Park – used a model organic semiconductor. The material has well-known properties, but with carrier mobility values of 1.6 cm2/Vs isn’t the fastest available. As a next step, they researchers would like to test their process on newer organic semiconductors that provide higher charge mobility. They also plan to continue testing the nanolaminate under different bending conditions, across longer time periods, and in other device platforms such as photodetectors.

Though the carbon-based electronics are expanding their device capabilities, traditional materials like silicon have nothing to fear.

“When it comes to high speeds, crystalline materials like silicon or gallium nitride will certainly have a bright and very long future,” said Kippelen. “But for many future printed applications, a combination of the latest organic semiconductor with higher charge mobility and the nanostructured gate dielectric will provide a very powerful device technology.”

This research was supported in part by the Center for Organic Photonics and Electronics at Georgia Tech, by the Department of the Navy, Office of Naval Research Awards N00014-14-1-0580 and N00014-16-1-2520, through the MURI Center for Advanced Photovoltaics (CAOP), by the Air Force Office of Scientific Research through Award No. FA9550-16-1-0168, by the National Nuclear Security Administration Award DE-NA0002576 through the Consortium for Nonproliferation Enabling Technologies (CNEC). Seminal work on the concept of using a bilayer gate dielectric in OFETs was funded in part by Solvay S.A. and described in part in issued patent No. US 9,368,737 B2.

CITATION: Xiaojia Jia, Canek Fuentes-Hernandez, Cheng-Yin Wang, Youngrak Park, Bernard Kippelen, “Stable organic thin-film transistors,” (Science Advances, 2018). 

Research News
Georgia Institute of Technology
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Media Relations Contacts: John Toon (404-894-6986) (jtoon@gatech.edu) or Josh Brown (404-385-0500) (josh.brown@comm.gatech.edu)

Writer: John Toon

Su is a May 2018 Ph.D. graduate of the Georgia Tech School of Electrical and Computer Engineering (ECE) and now works at Google as a hardware engineer. She joined the ATHENA Lab in fall 2013, where she was advised by Manos Tentzeris, who holds the Ken Byers Professorship in Flexible Electronics. She received her bachelor’s degree in Electrical Engineering from Beijing Institute of Technology in summer 2013 and her master's in ECE at Georgia Tech in May 2015.

Su's Ph.D. research focuses on interface advanced novel fabrication techniques such as inkjet-printing and 3D printing, and special mechanical structures such as microfluidics and origami. She also works on high-performance microwave components/antennas to solve existing problems and extend to applications in smart health, wearable electronics in Internet-of-Things (IoT) applications. Su specifically focuses on designing novel reconfigurable antennas/microwave passives components using dielectric liquid, as well as liquid metal alloy, and building liquid sensors/sensing platforms for easier communication and better sensing.

A potential strategy to overcome this barrier is to introduce new materials into the transistor structure to enhance their performance and functionalities. And that is the playground of Professor Asif Khan’s group of the School of Electrical and Computer Engineering at the Georgia Institute of Technology. “One of the interesting classes of functional materials that we are working on is called antiferroelectric oxides, which could lead to efficient, nanoscale logic and memory devices and devices which can even mimic the functions of biological neurons and synapses,” says Khan. In their recent work published as an Editor’s Pick in the May issue of Applied Physics Letters, they show how these mystery materials—antiferroelectrics—can be fine-tuned by doping, and how their processing techniques can be simplified to ease their entry into conventional micro- and nano-electronic fabrication technologies.

Antiferroelectric materials are electrical insulating in a way very similar to the dielectric materials used in regular capacitors. However, the significant difference is that when a certain voltage is applied across it, it undergoes a phase transition into another  insulating state which is structurally different than the parent one. With appropriate nano-scale engineering, this phenomenon can be the basis for high performance logic transistors and disruptive memory technologies. Interestingly, antiferroelectricity was discovered more than 60 years ago in perovskite materials—yet it did not have a significant impact on the electronics industry despite the attractiveness because perovskites are not compatible with currently used CMOS fabrication processes. What makes the Khan group’s work particularly relevant for transistor applications is that they are studying this phenomenon in Zirconia--a very well-studied non-perovskite binary oxide which has already been in use for more than a decade in the semiconductor industry.

The major contribution of the recent work by Khan’s group is that they significantly simplified the complex process flow of stabilizing the antiferroelectric phase of zirconia. Typically, a metallic capping layer and a high temperature annealing step is required to convert dielectric zirconia into an antiferroelectric state. The group were able to eliminate these process steps through a thoughtful design process of the material stack. Khan is hopeful that this will reduce the barrier to entry of antiferroelectrics into the state-of-the-art semiconductor manufacturing processes for novel device applications. Furthermore, by introducing small amounts of lanthanum into zirconia, the researchers were able to tune the properties of antiferroelectric zirconia, namely critical field/voltage for phase transition, dielectric constant and polarization. “Such tunability can not only enable a large design space for nanoelectronic antiferroelectric devices, but also be useful for their traditional applications of antiferroelectrics in electro-calories, pyroelectrics and micro-actuators,” says Khan. He also mentions that antiferroelectricity is a close cousin of a well-known phenomenon—ferroelectricity, which being researched and adopted by major semiconductor manufacturers for potential memory applications. His previous work also focused on ferroelectric oxides for ultra-low power negative capacitance transistors. However, as he points out, antiferroelectric oxides can do all that ferroelectric oxides can but with much better endurance and reliability and reduced process complexity.

Khan’s group actively collaborated with their industry partner, Eugenus, Inc. located in San Jose, CA. “Our industry-academia partnership is vital for bringing new ideas into the fore-fronts of technology,” says Dr. Mukherjee of Eugenus, Inc., also a co-author of the paper.  “We look forward to further collaboration to assess the applicability and the potential of new material and device concepts.” The Khan group also collaborated with the Charles University at Prague, Czech Republic, on structural characterization of the antiferroelectric zirconia films.

- Christa M. Ernst

“Antiferroelectricity in lanthanum doped zirconia without metallic capping layers and post-deposition/-metallization anneals” is an Editor’s Pick in May’s Applied Physics Letters. You can view the article here. https://aip.scitation.org/doi/10.1063/1.5037185

Khan’s work at Georgia Tech is supported in part by the National Science Foundation.

Over the course of five years, this grant program has seeded forty-five projects with forty-nine students working in ten different schools in COE and COS, as well as the Georgia Tech Research Institute and 2 external projects.

The 4 winning projects, from a diverse group of engineering disciplines, were awarded a six-month block of IEN cleanroom and lab access time. In keeping with the interdisciplinary mission of IEN, the projects that will be enabled by the grants include research in materials, biomedicine, energy production, and microelectronics packaging applications.

The Spring 2018 IEN Seed Grant Award winners are:

• Jiang Chen (PI Ben Wang - MSE): Validation and Characterization of Living Cell Grafting on Polycaprolactone Fibers for Textile Tissue Engineering
• Fatima Chrit (PI Alexander Alexeev - ME): Microfluidic Adhesion-based Sorting of Biological Cells
• Zifei Sun (PI Gleb Yushin - MSE): FeOx Coated FeF3-C Nanofibers as Free-standing Cathodes for Sodium- Ion Batteries
• Ting Wang (PI Xing Xie - Civil and Environmental Engineering): Development of Lab-on-a-Chip Devices for the Mechanisms Study of Cell Transportation and Bacteria Inactivation in a Non-Uniform Electric Field

Awardees will present the results of their research efforts at the annual IEN User Day in 2019.

With billions of connected devices, and several more billions to come in the next few years, the opportunities are endless.  With such a dramatic growth, the devices need to be low-cost, preferably self-powered, low power-consuming, wirelessly connectible, reliable, mass producible, customizable, easily accessible and usable, lightweight, and also be able to conform to the surface of the object to which they are attached.  This conformality then drives the need for flexible electronics, changing the world of electronics from one of being flat and stiff to one which is bendable and stretchable. This paradigm shift in electronics, driven by the shape of things-to come drives the need for Flexible Hybrid Electronics (FHE).

With these grand challenges in mind, Prof. Suresh Sitaraman from the George W. Woodruff School of Mechanical Engineering and the Institute for Electronics and Nanotechnology (IEN) , Georgia Tech hosted, in conjunction with NextFlex, the Flexible Hybrid Electronics Manufacturing Innovation Institute, a workshop that focused on expert presentations of state-of-the-art, along with the  defining a technical roadmap targeting on the power aspects of FHE device, called “Powering the Internet of Everything”.

The workshop, attended by nearly 90 Government, Industry, and Academic experts was held in the Marcus Nanotechnology Building on November 6 – 8, 2017. The three-day event included invited talks, roadmapping, a student technical poster session, and guided tours of principal research and shared user laboratories where FHE related research, micro/nano fabrication and microanalysis occur on the GT campus. Labs visited included mechanical and electrical testing, modeling and characterization; additive and 3D printing; device packaging; soft robotics and exoskeleton; organic photonics and electronics; and the IEN micro/nano fabrication and microscopy laboratories, to name a few. Workshop attendees were able to get up a close up view to the interesting FHE projects in which students and faculty are engaged. At each stop in the tour students demonstrated their work and answered questions about their programs, from flexible batteries for IOT to robotic human augmentation exoskeletons, FHE-enabled wearables and human-machine interfaces, and more.  Of greatest interest to the participants were those technologies that had already been demonstrated in the GT labs and which are ready for prototyping and pilot scale manufacturing.

Technical sessions included; Power and Energy Systems Needs, Energy Harvesting Strategies, Energy Storage Strategies, Power Management Strategies, and Ultra-Low Power Electronics/Sensors. Speakers were drawn from both government and private sectors, as well as academia. Speakers included participation from AT&T, IBM, NIH, Naval Surface Warfare Center, the Office of Naval Research, PARC, Silniva, Air Force Research Lab, Oak Ridge National Laboratory, Blue Spark Technologies, Analog Devices, Texas Instruments, and the Georgia Institute of Technology.

Following the technical sessions, the Marcus Nanotechnology Building Atrium space filled to capacity for an evening reception and competitive student poster and demo session. With over 35 FHE projects on display, the judging team consisting of industry and government experts was challenged with determining the best posters based on the content, clarity and organization, and overall presentation. After the scores were tallied, it was announced that there was a three-way tie for first place, a second place winner, and a tie for third, with all of them winning monetary awards.

Below is a list of the winning poster titles and authors:

Tied for 1^st

“Toward all-soft and fully-integrated microsystems: vertically integrated physical and chemical microsystems using gallium-based liquid metal and soft lithography”, Min-gu Kim and Prof. Oliver Brand

“Novel Architectures for Polymer Thermoelectric Devices for Energy Harvesting”, Akanksha Menon, Kiarash Gordiz, and Prof. Shannon Yee

“Soft, Fluidic Modulation of Skin Temperature”, Donald J. Ward, Nil Z. Gurel, Prof. Omer T. Inan, and Frank L. Hammond

2^nd Place

“Self-powered Wide-frequency Flexible Triboelectric (SWIFT) Microphone”, N. Arora, S. L. Zhang, M. Gupta, F. Shahmiri, D. Osorio, Y. Wang, Z. Wang, C. Zhang, T. Starner, B. Boots, ZL Wang, G. D. Abowd

Tied for 3^rd

“Mm-wave Ultra-Long-Range Energy-Autonomous Printed RFID      Van-Atta Wireless Gas Sensors: at the Crossroads of 5G and IoT”, Jimmy Hester and Prof. Manos Tentzeris

“Sensorized Pneumatic Muscles for Force and Stiffness Control”, Lucas O. Tiziani, Thomas W. Cahoon, and Frank L. Hammond III

About FHE at Georgia Tech:
Led by Prof. Suresh Sitaraman, the George W. Woodruff School of Mechanical Engineering, more than 30  researchers at Georgia Tech are involved in projects involving flexible electronics from the School of Mechanical Engineering, the School of Electrical and Computer Engineering, the School of Materials Science and Engineering, the H. Milton Stewart School of Industrial & Systems Engineering, the School of Chemical and Biomolecular Engineering, and the Wallace H. Coulter Department of Biomedical Engineering at Georgia Tech and Emory University. Several interdisciplinary research institutes at Georgia Tech are also involved in the projects, including the Institute for Electronics and Nanotechnology, Georgia Tech Manufacturing Institute, and the Institute for Materials.  The Office of Industry Collaboration and the College of Engineering are also actively engaged.

About NextFlex:
Formed in 2015 through a cooperative agreement between the US Department of Defense (DoD) and FlexTech Alliance, NextFlex is a consortium of companies, academic institutions, non-profits and state, local and federal governments with a shared goal of advancing U.S. Manufacturing of FHE. By adding electronics to new and unique materials that are part of our everyday lives in conjunction with the power of silicon ICs to create conformable and stretchable smart products, FHE is ushering in an era of “electronics on everything” and advancing the efficiency of our world.

- Christa M. Ernst
  {christa.ernst@ien.gatech.edu}

The 4 winning projects, from a diverse group of engineering disciplines, were awarded a six-month block of IEN cleanroom and lab access time. In keeping with the interdisciplinary mission of IEN, the projects that will be enabled by the grants include research in materials, biomedicine, energy production, and microelectronics packaging applications.

The Fall 2017 IEN Seed Grant Award winners are:

• Saswat Mishra (PI Woon-Hong Yeo, Woodruff School of Mechanical Engineering), Stretchable Hybrid Electronics for Wireless Monitoring of Salivary Electrolytes Assays
• Arith Rajapakse (PI Anna Erickson, Woodruff School of Mechanical Engineering), Ionizing Radiation Detection Using a Vertically Aligned Carbon Nanotube Array Transistor
• Nujhat Tasneem (PI Asif Khan, Electrical and Computer Engineering), Co-integration of Logic and Non-volatile Memory in Front-End-of-the-Line (FEOL) Processes
• Congshan Wan (PI Muhannad Bakir and Tom Gaylord, Electrical and Computer Engineering), First Circular Waveguide Grating-Via-Grating for Interlayer Optical Coupling

Awardees will present the results of their research efforts at the annual IEN User Day in 2018.

For more information about IEN cleanroom facilities, research capabilities, and collaboration opportunities please visit www.ien.gatech.edu.

Electromagnetic interference (EMI) is defined as unwanted electrical or magnetic coupling between components in a module or system. Such coupling or cross-talk results to performance degradation and electromagnetic compatibility issues. With increased multi-functional integration and miniaturization of emerging consumer, IoT, and automotive electronics, component-level EMI shielding has become extremely important to prevent undesired electromagnetic (EM) coupling.

EMI noise in traditional modules with large components is shielded by metallic cans or creating physical separation between them. Shielding with conformal metal coatings on overmolded packages has also been demonstrated. Component-level shielding has been developed with integrated via-based shields inside packages.

In contrast to the prior approaches described above, Georgia Tech team has recently pioneered innovative multi-layered structures for more effective EMI shielding. In the near field region, magnetic fields, generated from sources such as power inductors and transformers, have lower wave impedance and hence are difficult to be shielded with blanket sheets of a few micron thickness. To address this challenge, unique thin magnetic-nonmagnetic multi-layered structures, which lead to high shielding effectiveness, are developed. The primary shielding mechanism for such thin multi-layered shields is the multiple reflections that occur at interfaces between magnetic and conductive thin layers because of impedance mismatch. Furthermore, by employing copper as a conductive material, absorption loss also contributes to high shielding effectiveness.

The Georgia Tech team, in partnership with Tango Systems, has demonstrated this concept with ultra-thin (< 5 micron) multi-layered shield composed of copper (Cu), titanium (Ti), and nickel-iron (permalloy) for noise suppression of 100 kHz to 100 MHz from DC-DC converters as an example. In this frequency range, such multi-layer shields placed between two magnetic coils show higher isolation or less near-field inductive coupling than traditional shielding materials such as copper or nickel films. Multi-layered structures composed of Ti, Cu, and NiFe showed 59 dB isolation, or more than 20 dB shielding effectiveness, much greater than NiFe-Cu shield or the NiFe-Ti multi-layered structures. This approach is now extended for further improvement in shielding effectiveness performance by employing oxide layers such as alumina within the multi-layered structures.

In addition to those multi-layered shielding materials, Georgia Tech team has also been pioneering package-integrated copper via-trench structures for component-level shielding between sensitive RF components. Such shields are now custom-designed for isolation between transmission lines, RF inductors, also RF power amplifiers. Since undesired EM coupling occurs both from above and below the substrates, innovative trench shielding structures with through-substrate vias or micro-vias are designed and demonstrated with 2-4 GHz shielding of above 65 dB even with component separation of below 0.5 mm. Georgia Tech is now extending these trench-via array and multi-layered conductor structures to 5G and other mm-wave modules in the frequency range of 28 GHz to 39 GHz.

This research is being performed in partnership with a large global team of material and tool companies and with support from several on-site industry engineers at Georgia Tech.

This project is part of Georgia Tech industry consortium in System Scaling which includes about 40 end-user and supply chain companies and RF module companies.

About the Authors

Atom Watanabe is an ECE student pursuing his PhD under the advisement of Prof. Rao Tummala. His research focus is on 5G modules with advanced shielding structures. atom@gatech.edu 

Dr. P.M. Raj is the Program Manager for Integrated Passive and Actives as well as High-Temp Electronics at Georgia Tech PRC. raj@ece.gatech.edu

Prof. Rao Tummala is Joseph. M. Pettit Chair Professor in ECE and MSE and Director of Georgia Tech’s Packaging Research Center. rao.tummala@ece.gatech.edu.

High-temperature performance of molding compounds is becoming a key bottleneck for least three reasons: 1) integrated power modules with wide-bandgap (WBG) switches, gate drivers and controllers with ultra-high power densities, leading to escalating package temperatures; 2) under-the-hood automotive electronics; and 3) improvements in molded wafer and panel fan-out packages to address die drift, shrinkage and warpage issues.

Traditional molding compounds are limited to temperatures below 175°C. Although a number of polymer materials such as polyimide, cyanate ester, and benzocyclobutene (BCB) polymers offer high-temperature stability, epoxies are still the preferred choice because of several advantages that include excellent interfacial adhesion, low moisture absorption, excellent molding processibility and low cost. Recent advances include incorporation of multi-aromatic structures in the epoxy resin to enhance thermal stability of the cured composite. However, undesirable changes in material properties such as resin decomposition and the loss of volatile species become inevitable. Loss in mechanical toughness and oxidative-degradation still remain as the other major limitations with epoxies.

The Georgia Tech team, which includes polymer chemists, package processing and reliability experts, is developing higher temperature molding compounds with higher thermal stability stability, higher thermal conductivity, enhanced fracture toughness, and improved resistance to oxidative-degradation. Thermal stability of epoxies is being enhanced by incorporating thermally-stable functionalities derived from cyanate esters. The thermal conductivity of molding compounds is being enhanced with functionalized boron nitride fillers, while the fracture toughness of molding compounds is being enhanced with rubber-coated silica fillers that serve as crack-energy absorbers. The simultaneous synergy of enhancing the thermal stability, thermal conductivity and crack resistance provides unique opportunities to develop high-performance epoxy molding compounds to address some of the limitations of current wafer and panel fan-out packages as well as emerging high-power automotive electronics.

In addition to synthesizing the high-temperature molding compounds, the ongoing project will also focus on thermo-mechanical reliability including fracture characterization at various material interfaces up to 250°C. Thermo-mechanical models are also being used to determine stress/strain distribution as well as energy available for crack propagation in packages that use high-temperature mold compounds. Such models will be used to obtain design guidelines for high-temperature applications.

This project is part of Georgia Tech industry consortium in System Scaling which includes about 40 end-user and supply chain companies.

About the Authors

Chia-Chi Tuan is a PhD student under the advisement of Prof. CP Wong. Her research focus is on epoxy-based polymer composites. chiachituan@gatech.edu.

Dr. Jack Moon is a Research Engineer at the School of Materials Science and Engineering at Georgia Tech. jack.moon@gatech.edu.

Prof. CP Wong is the Regents' Professor and Smithgall Institute Endowed Chair at the School of Materials Science and Engineering at Georgia Tech. cp.wong@mse.gatech.edu.

Prof. Suresh Sitaraman is Morris M. Bryan Jr. Professor with George W. Woodruff School of Mechanical Engineering at Georgia Tech. suresh.sitaraman@me.gatech.edu.

Dr. Raj Pulugurtha is a Research Professor and Program Manager of RF, Power and High-Temperature Materials at GT PRC. raj.pulugurtha@ece.gatech.edu.  

Prof. Rao Tummala is Joseph. M. Pettit Chair Professor in ECE and MSE and Director of Georgia Tech’s Packaging Research Center. rao.tummala@ece.gatech.edu.

Advanced polymer materials are the key to high density packaging by enabling ultra-small vias and wiring layers to achieve 50 ohm impedance RDL wiring layers.

Traditional polymer dielectrics are thicker films (>20µm) and thus are unsuitable to RDL wiring layers at fine pitch and at 50 ohm impedance. Although liquid spin-on polymers such as Polyimide and PBO have been used widely in wafer level packaging, such materials are difficult to apply as thin dry films on large panels.

In contrast to these materials, Georgia Tech and its industry partners have been developing ultra-thin (3-10µm) dry film polymer materials and associated RDL via and line formation processes. Ultra-thin polymer dry films provide added benefits of better thickness control, improved planarization on underlying copper, large panel processing, and environmental friendliness. The Georgia Tech program involves a number of material partners in photo-sensitive from TOK Japan, dry film BCB from Dow Chemical, as well as non-photo dry film dielectrics from Ajinomoto Japan. The Georgia Tech programs that benefit from these polymer dielctrics include all digital applications using glass, advanced laminates and ceramic substrates.

The Georgia Tech team has demonstrated wafer and panel substrates with 2µm lines and spaces by advanced semi-additive processes (SAP) using 7µm thin dry film photo resists and projection lithography tool provided by Ushio Japan. Wafer and panel metallization was performed using a 300 mm panel plating line at Georgia Tech installed by Atotech, Germany. Various approaches are being investigated to demonstrate ultra-small micro-vias below 10µm including solid state UV laser, using a CornerStone™ system installed at Georgia Tech by ESI, excimer laser ablation supported by Suss Photonic Systems, photo lithography processes with advanced dry films provided by TOK Japan, Dow Chemical and other partners. By combining these materials and processes, multi-layer structures with 10µm vias and 2.5µm lines and spaces were successfully demonstrated to fabricate a 2.5D logic-HBM emulator designed with guidance from IBM/GlobalFoundries, AMD, Intel and others (top figure).

To address the limitations of SAP processes in pitch scaling,a novel via-in-trench (VIT) and via-in-line (VIL) embedded trench+via methods have been invented and demonstrated to achieve ultra-small liness and vias on large panels. Advantages of the embedded approach are the elimination of seed etching processes and the formation of conductive wires with higher aspect ratios for better electrical conductivity. Two different approaches are studied in the Georgia Tech program; excimer laser ablation by Suss Photonic Systems with non-photo polymer dielectrics and photolithography with photo-polymers. After the trench and via formation, trench and via fill plating from Atotech and a low-cost surface planarization process (tool installed at Georgia Tech by Disco Japan) to remove copper overburden were used to metallize the fine pitch RDL. Using this approach, 2µm lines and spaces with embedded vias have been successfully demonstrated (bottom figure).This is one of the first demonstrations of silicon-like RDL that Georgia Tech team achieved using glass panels with potential for lower cost Cu-polymer RDL materials and processes.

This research is being performed in partnership with a large global team of material and tool companies and with support from several on-site industry engineers at Georgia Tech.

This project is part of Georgia Tech industry consortium in System Scaling which includes about 40 end-user and supply chain companies.

About the Authors

Yuya Suzuki is a PhD student under the advisement of Prof. Rao Tummala. His research focus is on thin film dielectrics and small micro-vias. ysuzuki3@mail.gatech.edu.

Fuhan Liu is the Assistant Program Manager for Electronic and Photonic Substrates at Georgia Tech PRC. fliu@ece.gatech.edu

Dr. Venky Sundaram is the Program Manager of Substrate Programs and Associate Director of Industry Programs at Georgia Tech PRC. vs24@mail.gatech.edu

Prof. Rao Tummala is Joseph. M. Pettit Chair Professor in ECE and MSE and Director of Georgia Tech’s Packaging Research Center. rao.tummala@ece.gatech.edu.

The explosive growth of data traffic from increasing number of digital and sensor devices, connected to the network, and the escalating demand for self-driving cars requiring both long-range vehicle-to-network and short-range vehicle-to-vehicle connectivity, has created a need for 10-100X increase in wireless data communication rates beyond current 4G LTE connectivity. This extreme traffic density requires high-frequency mobile bands, much beyond WLAN at 6 GHz, requiring mm-wave (e.g., 28-39 GHz and above) communications. Many challenges in achieving these goals such as those associated with system-level design, materials, processes, antennas and module integration must be addressed.

Traditional mm-wave packages are based on ceramic substrates. The high cost and low-integration limitations of ceramics have led to the evolution of organic packages. A fully-integrated antenna-in-package (AiP) for W-band phased-array system, with 64 dual-polarization antennas embedded in a multi-layer organic substrate, with SiGe transceiver dies that are flipchip-attached has been demonstrated by IBM. In addition, ultra-low loss organic substrates using Teflon and LCPs were explored with high gains and high bandwidth. The evolution of embedded and fan-out wafer level ball grid array package technology (eWLB) further enhanced the performance of mm-wave packages by eliminating the wirebonds, as demonstrated by Infineon technologies, with SiGe-BiCMOS technology. However, organic laminates and molding-compound based fan-outs are limited by the precision and tolerance of circuitry for mm-wave components.

In contrast to the above approaches for 5G and beyond, Georgia Tech and its industry partners are pioneering ultra-thin, panel-based glass fan-out (GFO) embedded technology. GFO offers many advantages such as low electrical loss, superior dimensional stability for precision circuitry, stability to high temperature and humidity, matched CTE to Si and other devices and availability in thin and large glass panels processed with Cu-through vias, similar in dimensions to TSVs and RDL wiring layers, and similar to BEOL on Si. The Georgia Tech approach leads to major design, material, process and 3D package architecture innovations.

Some of the key research innovations of the Georgia Tech 5G and beyond program include:

1. Low-loss transmission with innovative waveguide structures on glass substrates with insertion losses approaching 0.05 dB/mm.
2. Formation of precision circuitry enabled by high dimensional stability and surface smoothness of glass resulting in further lowering of the losses.
3. Miniaturized and high bandwidth, high gain antenna arrays enabled by glass, in combination with ultra-low loss thinfilm polymers with initial results indicating that the bandwidth can be improved by 20% with a gain of 10 dBi than those on organic substrates.
4. Formation of via arrays in glass with double-side interconnections enabling compact passive elements such as couplers and filters.
5. Integrated power amplifiers with thermal management using large copper through-via structures in glass thus eliminating the hotspots and reliability issues with embedded high-power dies.
6. Feasibility of transparent RF electronics enabled by transparent glass substrates, transparent dielectrics and conductors in automotive windshields and windows.
7. Innovative materials and processes such as 3D printing on flex substrates being pioneered by Georgia Tech for low-cost IoT applications.
8. Innovative module integration of passives and actives with ultra-short interconnection length and ultra-small-vias in glass, resulting in very low via inductance, less than 50 pH and via-related transition losses, to less than 0.03 dB.

The 5G project is currently active in collaboration with many industry partners, including glass companies such as Corning Glass, Asahi Glass, and Schott Glass, supplying the ultra-thin glass panels; low-loss dielectric material suppliers such as Rogers; tool companies such as Ushio for precision lithography; Disco for planarization and dicing; Atotech for supplying the plating chemistry for advanced metallization processes; and end-users like Qualcomm. 

About the Authors

Atom Watanabe is a PhD student under the advisement of Prof. Rao Tummala. His research focus is on EMI shielding and mm-wave module integration; atom@gatech.edu.

Prof. Manos Tentzeris, Ken Byers Professor in ECE Department, Georgia Tech, is the faculty lead for the mm-wave program; etentze@ece.gatech.edu.

Prof. Rao Tummala is the Joseph M. Pettit Chair Professor in ECE and MSE, and the Director of Georgia Tech’s 3D Systems Packaging Research Center (GT PRC); rao.tummala@ece.gatech.edu.

Dr. Raj Pulugurtha is a Research Professor and the Program Manager of Power and RF Module Programs; pm86@mail.gatech.edu.

Dr. Venky Sundaram is a Research Professor and the Program Manager of Glass Substrate Program; vs24@mail.gatech.edu.

The proliferation of mobile devices, feeding the data to the cloud, has resulted in an unprecedented increase in global data traffic; projected to double to about six Exabytes (10¹⁸) per day by 2020. Electrical interconnects are limited for many reasons including device leakage, propagation delay, signal-to-signal crosstalk, reflection and others. Optical interconnects are immune to these and being photonic-based, are capable of meeting the above high bandwidth requirements. Unlike in long-distance telecommunications, short-distance bandwidth requires careful balance between performance, power and cost.

Silicon photonics and board-level optoelectronics are being intensely explored by the industry. Silicon photonics promises the highest potential by combining photonics and electronics onto a single die, using CMOS-compatible processes. Board-level optoelectronics, on the other hand, utilize low-cost board substrate process technologies to create Optical Printed Circuit Boards (O-PCB).

In contrast to these above approaches, Georgia Tech proposed and developed a very innovative 3D glass photonics (3DGP) technology, not at device or board-level, as with silicon and board-level photonics, but at package-level. It is a lower cost and low power alternative to silicon photonics and board-level optoelectronics. In addition, it is a 3D concept using glass with an ultra-short photonic via interconnection. Glass offers a unique combination of optical, electrical, thermo-mechanical and dimensional-stability properties for precision alignments, and large-area panel processability for low cost, unmatched by other materials. Optically, the refractive index of glass can match that of glass optical fibers to enable low-loss light coupling. Electrically, the low-loss tangent of glass is far superior to that of silicon. Mechanically, the Coefficient of Thermal Expansion (CTE) of glass matches silicon and other devices, thus improving the system-level reliability. The low surface roughness and high dimensional stability of glass is capable of 1µm and below features similar to back end of line (BEOL) silicon processes, for high interconnect density and precise coupling to optical fibers. Lastly, glass has the potential for low cost by virtue of large panel manufacturing

Recently, Georgia Tech’s 3DGP program demonstrated a 400 Gbps optical transceiver module. This test vehicle featured optimized electrical interconnects at < 0.1 dB/mm insertion loss, thermal interconnects to keep laser temperature under 80ºC, and novel optical interconnections comprising of planar optical waveguides, 3D vertical optical vias, 45º turning mirrors, and fiber alignment grooves in glass. These novel optical interconnections resulted in < 2 dB coupling loss with high-density out-of-plane turning, and alignment tolerance on par with fiber-to-fiber coupling.

The Georgia Tech industry consortium is unique in the academic world. It involves partnership with end-user and supply chain companies, resulting in accelerated 3DGP technology development. The end-users include TE Connectivity and Ciena Corp.; and supply chain companies include Corning Glass, Asahi Glass, and Schott Glass for supplying the ultra-thin glass panels with vias or cavities; Dow-Chemical for polymers; Ushio for placing a lithographic tool at Georgia Tech to enable micro-mirror formation; Atotech for supplying the chemistry for advanced metallization processes; Microchem for supplying optical polymers; and DISCO for placing a dicing tool at Georgia Tech to enable fiber alignment groove formation.

About the Authors

Bruce Chou, is graduating in Fall 2016 with his PhD under the advisement of Prof. Rao Tummala. His research focus is on Design and Demonstration of 3D Glass Photonics. cchou36@gatech.edu.

Prof. Rao Tummala is Joseph. M. Pettit Chair Professor in ECE and MSE and Director of Georgia Tech’s Packaging Research Center. rao.tummala@ece.gatech.edu.

Dr. Fuhan Liu is a Research Professor and Program Manager of Glass Photonics Program at GT PRC fuhan.liu@ece.gatech.edu.

Dr. Venky Sundaram is a Research Professor and Associate Director of Industry Programs at GT PRC vs24@mail.gatech.edu. 

All packages are fan-out packages with the exception of chip-scale or wafer-level packages. These fan-out packages fall into two categories: chip-first, also called embedded, and chip-last. Both provide wiring or RDL to connect to ICs at fine or coarse pitch. In the chip-first approach, RDL is deposited directly onto ICs thus requiring no assembly; in contrast, in the chip-last process, two separate processes, one to form RDL with or without a substrate and second to assemble ICs to the wiring layers.

Fan-out wafer-level packages (FO-WLP), as extension of wafer-level packages, provide RDL wiring and I/Os beyond ICs on the surface of molding compounds. These packages, therefore, are no longer limited by I/Os and are thus poised to disrupt the entire semiconductor industry due to their benefits in performance, due to ultra-short interconnections, and wafer-based manufacturing infrastructure availability, compared to traditional flip-chip or wire bond packages. Two sets of applications are driving the need for fan-out packages: 1) analog applications that include RF, mm-wave such as Radar, and power for consumer electronics, using smaller and thinner devices to achieve thin packages with high component densities; and 2) digital applications to embed processors with larger ICs at higher I/O densities. The scope of FO-WLP technology is being proposed and developed in recent years to include multi-component SiP modules and integrated logic and 3D memory stacks to achieve high bandwidth.

But wafer fan out, as practiced today, has three major limitations: High cost, small Package size and low I/O density. Cost and package size limitations are due to small 300 mm wafers from which these fan-out packages are produced and low I/O density due to molding compound-driven challenges.

To address some of these concerns, panel-fanout Packaging (FO PLP) is beginning to emerge as a major new frontier. The economies of scale of panel-based processing may reduce FO-WLP cost by as much as 2-4x, depending on the package size, with the number of dies per package, the number of RDL layers and the panel size. FO PLP technologies can be broadly classified into two categories: 1) PWB infrastructure-based panel fan-out such as Imbera’s Integrated Module Board (IMB), AT&S’s Embedded Components Packaging (ECP), and ASE’s advanced – Embedded Assembly Solution Integration (a-EASI); Amkor and J-Devices Wide Strip Panel Fan-out Package (WFOP); and 2) LCD infrastructure-based panel fan-out that include PTI’s molded fan-out using 370mm x 470mm panels, and most recently by Samsung LSI, Samsung Display and SEMCO by repurposing idled Gen 3.25 (600mm x 720mm) and Gen 4 (730mm x 920mm) LCD lines. 

Thev next generation of panel fan-out evolution must address three barriers:

1. Interconnect gap for digital applications
2. Thickness or miniaturization gap for analog, power, RF and mm-wave, and
3. Thermal and power gap for high-power applications.

Georgia Tech and its 50 industry partners are developing next generation of panel fan-out in both chip-first and chip-last approaches to address these barriers, not only for computing and communications applications, but also for high-temperature and high-power automotive applications. In contrast to the wafer fan-out with molding compounds and laminate-based panel fan-outs, both can generally be referred to as organic-based, Georgia Tech’s approach is based on inorganic panel fan-out, either with glass as GFO or poly-silicon fan-out as PSFO.

The Georgia Tech Glass Fan-out (GFO) approach addresses the interconnect gap with Si BEOL-like wiring, currently at 20 µm pitch. In addition, GFO provides lower interconnect loss, and higher board-level reliability even with large package sizes. The silicon-like dimensional stability of glass in large-panel manufacturing brings an unparalleled combination of ultra-high I/O density, ultra-high electrical performance, ultra-high reliability at low and high-temperature and low cost, not possible in molding compound-based or laminate-based fan-out technologies. With the low-loss of glass, being a factor of ~2-3x better than molding compounds, Georgia Tech’s GFO approach is ideal for RF and mm-wave modules. Unlike large high-density fan-out packages that require another package such as organic BGA package to connect to boards, GFO packages are designed to be directly SMT-attached to the board, enabled by the tailorability of the CTE of the glass panels and compliant interconnections. Lastly, the ultra-smooth surface and high dimensional stability of glass enables silicon-like RDL capability on large panels, for the first time, with less than 2µm critical dimensions (CD) for high density fan-out applications.

The GFO project is part of Georgia Tech’s industry consortium, supported by a number of industry partners, including Corning Glass, Asahi Glass, and Schott Glass that supply ultra-thin glass panels with cavities; Ushio that has placed a panel lithographic tool at Georgia Tech; Atotech that provides the plating chemistry for advanced metallization; and DISCO that has placed a low-cost planarization tool at Georgia Tech. End user applications for GFO in the Georgia Tech consortium include 5G, automotive camera and RADAR modules, low- and high-power modules, and logic-to-3D memory modules.

About the Authors

Tailong Shi is a PhD student under the advisement of Prof. Rao Tummala. His research focus is on Design and Demonstration of glass fan-out (GFO) packages for 77GHz automotive RADAR and Camera modules. tshi@gatech.edu.

Dr. Venky Sundaram is a Research Professor and the Associate Director of Industry Programs at Georgia Tech PRC. vs24@mail.gatech.edu.

Dr. Fuhan Liu is a Research Professor and an Assistant Program Manager for the GFO program. fuhan.liu@ece.gatech.edu. 

Dr. Vanessa Smet is a Research Professor and the Program Manager for the Interconnections & Assembly (I&A) and High-power program. vanessa.smet@prc.gatech.edu.

Prof. Rao Tummala is the Joseph M. Pettit Chair Professor in ECE and MSE, and the Director of Georgia Tech’s 3D Systems Packaging Research Center (GT PRC). rao.tummala@ece.gatech.edu.   

The 4 winning projects, from a diverse group of engineering disciplines, were awarded a six month block of IEN cleanroom and lab access time. In keeping with the interdisciplinary mission of IEN, the projects that will be enabled by the grants include research in materials, biomedicine, nanoelectronics, and packaging applications.

The Spring 2016 IEN Seed Grant Award winners are:

• Moez Aziz (PI Hua Wang, Electrical and Computer Engineering), Developing Cellular Sample Delivery and Isolation Techniques on the Integrated CMOS Nanoelectronic Platform
• Meredith Fay (PI Wilbur Lam, Biomedical Engineering), How Do White Blood Cells Talk to Each Other? Leveraging Microfabricated Systems to Investigate Direct Neutrophil-to-Neutrophil Communication
• Augustus Lang (PI John Reynolds, Chemistry and Biochemistry & Materials Science and Engineering), Electrofunctional Paper: Flexible Paper-Based Displays
• Amar Mohabir and Sterling Smith (undergraduate)(PI Mike Filler, Chemical & Biomolecular Engineering), Plasmonic-Phononic Hybrid Nanoparticles: New Materials for Extreme Infrared Light Focusing

Awardees will present the results of their research efforts at the annual IEN User Day in 2017.

For more information about IEN cleanroom facilities, research capabilities, and collaboration opportunities please visit www.ien.gatech.edu.

Georgia Tech’s 3D IPAC approach enables 2X shrinkage in X-Y form factor and 2X smaller in thickness than LTCC and organic modules.It also enables superior performance from high-Q LC integration with better than 5% tolerance from precision lithography in contrast to ceramic modules, lower-loss interconnections between components leading to insertion losses of <0.5 dB. Glass provides ultra-smooth and dimensionally-stable substrates for high-throughput and large-area (1000 mm) panel processing with low cost. These advances are expected to enable the miniaturization, integration, performance and cost demands for emerging 5G front-end modules and their convergence with IoT and automotive communications.

Georgia Tech proposed 3D Integrated Passive and Active Component (3D IPAC) based glass RF modules and 3D IPDs in 2013, for unparalleled miniaturization, performance and cost. The 3D IPAC RF Module starts with an ultra-thin substrate (30-100 microns) made of glass, with ultra-low electrical loss and ultra-short through-package vias for double-side assembly of active and passive components separated by only about 50 µm in interconnect length. Actives and passives are embedded or assembled double-side on the glass using ultra-short, low-temperature and fine-pith copper interconnections. The module also integrates thermal and shielding functions with innovative structures and materials.

Several technology breakthroughs were accomplished to demonstrate such RF IPDs and modules. High-density through-vias in bare glass were formed from unique via-machining techniques by Georgia Tech’s partners such as Corning and Asahi Glass. Innovative tools and processes were developed for large glass panel handling with thinfilm low-loss build-up dielectrics, in partnership with Georgia Tech’s consortium members such as Atotech, NGK-NTK, Shinko and Unimicron. Advanced 3D TPV-based inductor designs were developed for high Q and high-density inductors, while inorganic nanodielectrics and nanomagneto dielectrics were utilized for further miniaturization of capacitors, inductors and EMI shield structures. Precision panel-level lithography was achieved for accurate microwave impedance matching with less than 5% tolerance. Double-side assembly was also demonstrated with such ultra-thin glass substrates.

Georgia Tech’s 3D IPD-based diplexers are 4X thinner compared to traditional approaches, with similar performance. With advanced thinfilm and high-density passive components, and design innovations, much superior performance is targeted in the next phase of the R&D program from 2016-2018. Georgia Tech and its partners also demonstrated ultra-miniaturized LTE and WLAN modules with its 3D IPAC approach with double-side integration of LNA, switch and filters. Good model-to-hardware correlations were seen from the module characterization of LNA gain and entry-to-exit insertion loss, illustrating the performance benefits of 3D IPAC modules. In the next phase, Georgia Tech is extending this concept further to complete PAMiD module integration with integrated thermal and shielding structures for LTE FDD/TDD, 5G and mm wave applications.

For more information about Georgia Tech’s Integrated Passives and Actives, please contact Prof. Rao Tummala at rao.tummala@ece.gatech.edu or Dr. P.M. Raj at raj.pulugurtha@prc.gatech.edu.

About the Authors

Dr. Raj Pulugurtha is the Program Manager for Integrated Passive and Actives as well as High-Temp Electronics at Georgia Tech PRC. raj.pulugurtha@prc.gatech.edu

Dr. Rao Tummala is Director of Georgia Tech’s Packaging Research Center. He is also a Chaired Professor in ECE and MSE. rao.tummala@ece.gatech.edu. 

Georgia Tech was the first to start glass packaging five years ago as the next generation packaging technology after plastic or leadframe packaging in the 1970s, ceramic packaging in 1980s, and organic build-up in the 1990s. Georgia Tech proposed glass packaging as a superior packaging platform due to its improved electrical properties including low dielectric constant and low dielectric loss, thermal expansion match to silicon ICs, smooth surface finish, low moisture absorption, and availability in ultra-thin and large form factors without grinding. Georgia Tech identified and addressed three fundamental limitations of glass packaging that included low thermal conductivity, TSV-like through via formation at fine pitch and low cost, and mechanical brittleness.

Currently, Georgia Tech is designing and demonstrating glass packaging for a variety of applications including digital, RF, power, flexible electronics and automotive applications.

The goal of Georgia Tech’s 2.5D glass interposer is to serve high-performance computing markets including networks, graphics and as the interconnect platform for split SOCs, as announced by IBM, AMD and now Intel. These markets share a common set of system requirements—low latency, ultra-high interconnect density for ultra-high bandwidth, low-power interconnections, large package size, and low cost. Currently, silicon interposer is the only commercially-available technology that begins to address these system needs. Silicon interposers, while they provide suitable interconnect density, suffer from high signal losses due to dielectric and conductor losses and high cost due to small 300 mm size wafer processing and manufacturing, as well as the need for an organic BGA package between the interposer and system board. Organic interposers are being developed to overcome these limitations of silicon interposers, but are fundamentally limited in I/O density over the long term. Georgia Tech’s glass interposer, in contrast, is made up of 100 micron thin glass, which is available in large panel or roll-to-roll form, with through via at as low as 30 micron pitch and fine-pitch RDL with microvias at less than 10 microns—enabling 40 micron chip-level I/O pitch in development and 20 micron pitch in research.

Georgia Tech and its industry partners are designing and developing 2.5D glass interposer BGA packages with the following strategic advantages:

• High electrical performance achieved using low permittivity and low loss dielectrics to fabricate multilayer RDL wiring lines at 6 micron line pitch with 3 micron line lithography leading to 40 micron bump pitch, enabling short, high-density die-to-die interconnections with 0.12 dB/mm line insertion loss at 2 GHz.
• Low interconnect losses achieved by reducing dielectric and conductor losses using low loss dielectrics and thick copper conductive lines, compared to BEOL. As a result, line insertion losses for high-speed, off-package interconnects as low as 0.05 dB/mm are achieved—a 6X reduction compared to similar results reported with silicon interposers.
• High reliability using unique interposer fabrication and assembly technologies
• High density interconnections since glass behaves like silicon in its surface smoothness and dimensional stability in minimizing line lithography, line pitch and I/O pitch. The Georgia Tech program has recently demonstrated 3 micron wiring lines with via-in-pad technology at 40 micron I/O bump, targeting 20 micron pitch in 2016.

Direct board-level attachment of 2.5D glass interposer BGA: Unlike silicon interposer, which requires organic BGA for assembly to PCB, direct attachment of a glass interposer BGA to board has been demonstrated by the Georgia Tech team using a 18.5 mm glass BGA package size. The stresses due to CTE mismatch between the glass and board are managed by a variety of stress buffer approaches.

Cost: The cost of glass interposer package is expected to be similar to organic packages in high volume by utilizing large panels that are 5-10x larger than 300 mm silicon wafers. In addition to large panel processing to reduce cost, the Georgia Tech process uses low cost materials and dryfilm processes, double-side advanced semi-additive plating, large area lithography, high-speed plating, and panel scalable die assembly technologies.

The Georgia Tech glass packaging R&D is unique in the academic world. It involves partnership with manufacturing supply chain and end-user companies, resulting in accelerated 2.5D glass interposer package R&D. Corning and Asahi Glass, for example, have both developed high throughput roll-to-roll glass panel manufacturing as well as high throughput through-via processes and prepared them for volume manufacturing. Other supply chain manufacturing contributions to accelerate 2.5D fabrication development include: Ushio’s lithographic tool placed at Georgia Tech for 2 micron line lithography, SUSS MicroTec’s projection excimer laser ablation for microvias at less than 10 microns, Atotech’s differential seed layer etch for advanced SAP, as well as Shinko’s and Unimicron’s glass substrate prototype fabrication using panel manufacturing processes.

The current design and demonstration focus is the fabrication of low cost advanced RDL and TCB chip assembly processes, resulting in the first 2.5D glass interposer package prototype shown above.

The next focus is to apply this interposer technology for high bandwidth logic-to-memory applications working with semiconductor and system companies

For more information about Georgia Tech’s glass packaging technology, please contact Prof. Rao Tummala at rao.tummala@ece.gatech.edu.

About the Authors

Brett Sawyer, is a 4^th year ECE student pursuing his PhD under the advisement of Prof. Rao Tummala. His research focus is on Modeling, Design, and Fabrication of 2.5D Glass Interposer. bsawyer@gatech.edu.

Dr. Rao Tummala is Director of Georgia Tech’s Packaging Research Center. He is also a Chaired Professor in ECE and MSE. rao.tummala@ece.gatech.edu.

Dr. Venky Sundaram is Program Manager for Glass Substrate at GT PRC and research faculty in ECE. vs24@mail.gatech.edu. 

Now, researchers at the Georgia Institute of Technology and Oak Ridge National Laboratory (ORNL) have developed a new nondestructive technique for investigating these material changes by examining the acoustic response at the nanoscale. Information obtained from this technique – which uses electrically-conductive atomic force microscope (AFM) probes – could guide efforts to design materials with enhanced properties at small size scales.

The approach has been used in ferroelectric materials, but could also have applications in ferroelastics, solid protonic acids and materials known as relaxors. Sponsored by the National Science Foundation and the Department of Energy’s Office of Science, the research was reported December 15 in the journal Advanced Functional Materials.

“We have developed a new characterization technique that allows us to study changes in the crystalline structure and changes in materials behavior at substantially smaller length scales with a relatively simple approach,” said Nazanin Bassiri-Gharb, an associate professor in Georgia Tech’s Woodruff School of Mechanical Engineering. “Knowing where these phase transitions happen and at which length scales can help us design next-generation materials.”

In ferroelectric materials such as PZT (lead zirconate titanate), phase transitions can occur at the boundaries between one crystal type and another, under external stimuli. Properties such as the piezoelectric and dielectric effects can be amplified at the boundaries, which are caused by the multi-element “confused chemistry” of the materials. Determining when these transitions occur can be done in bulk materials using various techniques, and at the smallest scales using an electron microscope.

The researchers realized they could detect these phase transitions using acoustic techniques in samples at size scales between the bulk and tens of atoms. Using band-excitation piezoresponse force microscopy (BE-PFM) techniques developed at ORNL, they analyzed the resulting changes in resonant frequencies to detect phase changes in sample sizes relevant to the material applications. To do that, they applied an electric field to the samples using an AFM tip that had been coated with platinum to make it conductive, and through generation and detection of a band of frequencies.

“We’ve had very good techniques for characterizing these phase changes at the large scale, and we’ve been able to use electron microscopy to figure out almost atomistically where the phase transition occurs, but until this technique was developed, we had nothing in between,” said Bassiri-Gharb. “To influence the structure of these materials through chemical or other means, we really needed to know where the transition breaks down, and at what length scale that occurs. This technique fills a gap in our knowledge.”

The changes the researchers detect acoustically are due to the elastic properties of the materials, so virtually any material with similar changes in elastic properties could be studied in this way. Bassiri-Gharb is interested in ferroelectrics such as PZT, but materials used in fuel cells, batteries, transducers and energy-harvesting devices could also be examined this way.

“This new method will allow for much greater insight into energy-harvesting and energy transduction materials at the relevant length sales,” noted Rama Vasudeven, the first author of the paper and a materials scientist at the Center for Nanophase Materials Sciences, a U.S. Department of Energy user facility at ORNL.

The researchers also modeled the relaxor-ferroelectric materials using thermodynamic methods, which supported the existence of a phase transition and the evolution of a complex domain pattern, in agreement with the experimental results.

Use of the AFM-based technique offers a number of attractive features. Laboratories already using AFM equipment can easily modify it to analyze these materials by adding electronic components and a conductive probe tip, Bassiri-Gharb noted. The AFM equipment can be operated under a range of temperature, electric field and other environmental conditions that are not easily implemented for electron microscope analysis, allowing scientists to study these materials under realistic operating conditions.

“This technique can probe a range of different materials at small scales and under difficult environmental conditions that would be inaccessible otherwise,” said Bassiri-Gharb. “Materials used in energy applications experience these kinds of conditions, and our technique can provide the information we need to engineer materials with enhanced responses.”

Though widely used, relaxor-ferroelectrics and PZT are still not well understood. In relaxor-ferroelectrics, for example, it’s believed that there are pockets of material in phases that differ from the bulk, a distortion that may help confer the material’s attractive properties. Using their technique, the researchers confirmed that the phase transitions can be extremely localized.

They also learned that high responses of the materials occurred at those same locations.
Next steps would include varying the chemical composition of the material to see if those transitions – and enhanced properties – can be controlled. The researchers also plan to examine other materials.

“It turns out that many energy-related materials have electrical transitions, so we think this is going to be very important for studying functional materials in general,” Bassiri-Gharb added. “The potential for gaining new understanding of these materials and their applications are huge.”

This research was supported by the National Science Foundation (NSF) through grant DMR-1255379. A portion of this research was conducted at the Center for Nanophase Materials Sciences, which is a DOE Office of Science User Facility at ORNL. The content is solely the responsibility of the authors and does not necessarily represent the official views of the NSF or DOE.

CITATION: Rama K. Vasudevan, et al., “Acoustic Detection of Phase Transitions at the Nanoscale,” (Advanced Functional Materials, 2015). http://dx.doi.org/10.1002/adfm.201504407

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A professor in the Georgia Tech School of Electrical and Computer Engineering (ECE), Swaminathan received the award for his paper entitled, “Enabling Antenna Design with Nano-magnetic Materials Using Machine Learning.” His coauthors on the paper are his ECE faculty colleagues, Rao Tummala and Raj Pulugurtha, and his colleagues from the University of L’Aquila (Italy), Carmine Gianfagna and Giulio Antonini.

Magneto-dielectric materials enable antenna miniaturization. Since magneto dielectrics are synthesized from magnetic particles and polymer dielectrics, the dimensions of the particles and their volume fraction need to be controlled carefully to obtain the required antenna performance. In this paper, machine learning methods were used to determine the particle size and volume fraction to obtain the desired antenna properties such as gain, bandwidth, radiation efficiency, and resonant frequency.

Swaminathan holds the John Pippin Chair in Electromagnetics and is the director of the Interconnect and Packaging Center. He has been with Georgia Tech since 1994 and has been a member of the ECE faculty since 1997.

Anodes – the negative electrodes – based on silicon can theoretically store up to ten times more lithium ions than conventional graphite electrodes, making the material attractive for use in high-performance lithium-ion batteries. However, the brittleness of the material has discouraged efforts to use pure silicon in battery anodes, which must withstand dramatic volume changes during charge and discharge cycles.

Using a combination of experimental and simulation techniques, researchers from the Georgia Institute of Technology and three other research organizations have reported surprisingly high damage tolerance in electrochemically-lithiated silicon materials. The work suggests that all-silicon anodes may be commercially viable if battery charge levels are kept high enough to maintain the material in its ductile state.

Supported by the National Science Foundation, the research was reported September 24 in the journal Nature Communications.

“Silicon has a very high theoretical capacity, but because of the perceived mechanical issues, people have been frustrated about using it in next-generation batteries,” said Shuman Xia, an assistant professor in the George W. Woodruff School of Mechanical Engineering at Georgia Tech. “But our research shows that lithiated silicon is not as brittle as we may have thought. If we work carefully with the operational window and depth of discharge, our results suggest we can potentially design very durable silicon-based batteries.”

Lithium ion batteries are used today in a wide range of applications from hand-held mobile devices up to laptop computers and electric vehicles. A new generation of high-capacity batteries could facilitate expanded transportation applications and large-scale storage of electricity produced by renewable sources.

The challenge is to get more lithium ions into the anodes and cathodes of the batteries. Today’s lithium batteries use graphite anodes, but silicon has been identified as an alternative because it can store substantially more lithium ions per atom. However, storing those ions produces a volume change of up to 280 percent, causing stress that can crack anodes made from pure silicon, leading to significant performance degradation. One strategy is to use a composite of silicon particles and graphite, but that does not realize the full potential of silicon for boosting battery capacity.

In an effort to understand what was happening with the materials, the research team used a series of systematic nano-mechanical tests, backed up by molecular dynamics simulations. To facilitate their study, they used silicon nanowires and electrochemical cells containing silicon films that were about 300 nanometers in thickness.

The researchers studied the stress produced by lithiation of the silicon thin films, and used a nanoindenter – a tiny tip used to apply pressure on the film surface – to study crack propagation in these thin films, which contained varying amounts of lithium ions. Lithium-lean silicon cracked under the indentation stress, but the researchers were surprised to find that above a certain concentration of lithium, they could no longer crack the thin film samples.

Using unique experimental equipment to assess the effects of mechanical bending on partially lithiated silcon nanotires, researchers led by Professor Scott Mao at the University of Pittsburgh studied the nanowire damage mechanisms in real-time using a transmission electron microscope (TEM). Their in-situ testing showed that the silicon cores of the nanowires remained brittle, while the outer portion of the wires became more ductile as they absorbed lithium.

“Our nanoindentation and TEM experiments were very consistent,” said Xia. “Both suggest that lithiated silicon material becomes very tolerant of damage as the lithium concentration goes above a certain level – a lithium-to-silicon molar ratio of about 1.5. Beyond this level, we can’t even induce cracking with very large indentation loads.”

Ting Zhu, a professor in Woodruff School of Mechanical Engineering at Georgia Tech, conducted detailed molecular dynamics simulations to understand what was happening in the electrochemically-lithiated silicon. As more lithium entered the silicon structures, he found, the ductile lithium-lithium and lithium-silicon bonds overcame the brittleness of the silicon-silicon bonds, giving the resulting lithium-silicon alloy more desirable fracture strength.

“In our simulation of lithium-rich alloys, the lithium-lithium bonds dominate,” Zhu said. “The formation of damage and propagation of cracking can be effectively suppressed due to the large fraction of lithium-lithium and lithium-silicon bonds. Our simulation revealed the underpinnings of the alloy’s transition from a brittle state to a ductile state.”

Using the results of the studies, the researchers charted the changing mechanical properties of the silicon structures as a function of their lithium content. By suggesting a range of operating conditions under which the silicon remains ductile, Xia hopes the work will cause battery engineers to take a new look at all-silicon electrodes.

“Our work has fundamental and immediate implications for the development of high-capacity lithium-based batteries, both from practical and fundamental points of view,” he said. “Lithiated silicon can have a very high damage tolerance beyond a threshold value of lithium concentration. This tells us that silicon-based batteries could be made very durable if we carefully control the depth of discharge.”

In future work, Xia and Zhu hope to study the mechanical properties of germanium, another potential anode material for high-rate rechargeable lithium-ion batteries. They will also look at all-solid batteries, which would operate without a liquid electrolyte to shuttle ions between the two electrodes. “We hope to find a solid electrolyte with both high lithium ion conductivity and good mechanical strength for replacing the current liquid electrolytes that are highly flammable,” Zhu said.

“The research framework we have developed here is of general applicability to a very wide range of electrode materials,” Xia noted. “We believe this work will stimulate a lot of new directions in battery research.”

This research was supported by the National Science Foundation through grants CMMI-1300458, CMMI-1100205 and NSF-DMR-1410936. The content is solely the responsibility of the authors and does not necessarily represent the official views of the National Science Foundation.

CITATION: Xueju Wang, et al., “High Damage Tolerance of Electrochemically Lithiated Silicon,” (Nature Communications, 2015). (http://dx.doi.org/10.1038/ncomms9417).

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The Honorable Pranab Mukherjee, president of India, presented Swaminathan and 30 additional distinguished recipients with this honor on July 19 at the NITT campus, which is currently celebrating its 50-Year Golden Jubilee. Suresh Sitaraman, a professor in the George W. Woodruff School of Mechanical Engineering, was also recognized with the same award at this event.

Swaminathan received his bachelor of engineering degree in electronics and communications from NITT in 1985 and went on to earn his master’s and doctoral degrees from Syracuse University in 1989 and 1991, respectively. In addition to his accomplishments at Georgia Tech and IBM, Swaminathan was recognized for helping to shape the design aspects of packaging that have led to the development of system on package technologies around the world, including the creation of an electronic packaging program at NITT and the education of engineers and scientists in India from both the private and public sectors.

Swaminathan is a faculty member at Georgia Tech, where he currently holds the John Pippin Chair in Electromagnetics in the School of Electrical and Computer Engineering (ECE) and is the director of the Interconnect and Packaging Center. He also served as the deputy director of the Microsystems Packaging Research Center, a National Science Foundation-sponsored Engineering Research Center. Prior to joining Georgia Tech, he worked for IBM on the packaging for supercomputers.

As the leader of the Mixed-Signal Design Research Group in ECE, Swaminathan has graduated 35 Ph.D. and 17 M.S. students. He has published more than 400 technical articles, holds 27 patents, and has authored three books, all related to electronic packaging. He also co-founded and founded two spin-off companies, Jacket Micro Devices (JMD), which focused on integrated RF modules and substrates for wireless applications, and E-System Design, which focuses on the development of CAD tools for integrated 3D microsystems.

Swaminathan’s research has been recognized through numerous awards, including 16 best paper and best student paper awards, a Technical Excellence Award from Semiconductor Research Corporation in 2007, the IBM Outstanding Faculty Award in 2004 and 2005, the Georgia Tech ECE Outstanding Graduate Research Advisor Award in 2002, and the 2014 IEEE Components, Packaging, and Manufacturing Technology Society Outstanding Sustained Technical Excellence Award. A Fellow of the IEEE, Dr. Swaminathan has also served as the Distinguished Lecturer for the IEEE Electromagnetic Compatibility Society.

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In the group photo, Swaminathan is pictured in the top row, second from the left, while Sitaraman is in the middle row on the left end of the row.

Georgia Tech entered into a partnership with French governmental entities in 1990 to establish its first international campus in Metz, France. After two decades of innovative educational achievements, a world-class research presence was added in 2006 with the creation of the Georgia Tech-Centre National de la Recherche Scientifique (CNRS) Unité Mixte Internationale laboratory. 

Georgia Tech is now moving to the next critical stage of expansion of its global influence with the creation of an innovation platform, the Institut Lafayette. By providing access to a state-of-the-art technology infrastructure; by sharing world-class expertise in science and technology; and by offering business model validation and commercialization tools, the Institut Lafayette will showcase and underscore Georgia Tech’s capacity to help create a full regional ecosystem which can generate innovations of economic and social value for its international partners.

This expansion of Georgia Tech’s global footprint will increase its impact around the globe, and serve to bring the world to Georgia Tech and to the State of Georgia. The Institut Lafayette will create opportunities to establish alliances with universities, companies, and governmental and non-governmental entities whose goals and activities align with Georgia Tech’s strategic mission. This expansion will also significantly augment the teaching, research and entrepreneurial activities of Georgia Tech’s faculty, staff, alumni and students both in Atlanta and in Lorraine. The new facilities also expand the European activities of the Georgia Tech Center for Organic Photonics and Electronics (Georgia Tech-COPE). The Institut Lafayette is expected to serve as a catalyst for economic development in the region of Lorraine and to increase trade exchange opportunities with metropolitan Atlanta, and the State of Georgia.

Located adjacent to the existing Georgia Tech-Lorraine building, the brand new 25,000 square foot facility is comprised of offices, laboratories and a 5,000 square foot clean room, fully equipped with state-of-the-art nanofabrication tools to support innovations in optoelectronics and advanced semiconductor materials research. This facility will be managed by Georgia Tech faculty members who are world-renown experts in organic materials and semiconductors.

This innovation platform will provide a unique combination of research expertise, an advanced technology infrastructure, and an array of technology transfer services which will increase efficiency and accelerate technology transfer.  Its impact and effectiveness will be further enabled by leveraging the resources of Georgia Tech – The Georgia Tech Enterprise Innovation Institute (EI2) will provide expertise in technology transfer and commercialization, and the Institute of Electronics and Nanotechnology (IEN) will provide expertise in managing and operating high-technology infrastructures.

The Institut Lafayette was named after the Marquis de Lafayette, a French aristocrat and military officer who served as a major-general in the Continental Army under George Washington in the American Revolution.   It was in Metz in 1775 that the Marquis de Lafayette made the decision to commit himself to the cause of American independence.

Swaminathan was honored "for significant and sustained contributions that have helped shape the design aspects of packaging in the areas of power delivery, system on package technologies, and 3D integration."

A faculty member in the Georgia Tech School of Electrical and Computer Engineering since 1994, Swaminathan holds the John Pippin Chair in Electromagnetics, and he is the director of the Interconnect and Packaging Center. He previously served as the deputy director of the Microsystems Packaging Research Center from 2004-2008.

Swaminathan leads the Mixed Signal Design Group in ECE, where he and his team conduct research in computational electromagnetics, multi-physics modeling, computer-aided design, 3D integration, nano materials, microwave design, RF sensors, and high-speed signaling.

He has published more than 400 technical articles, holds 27 issued patents, and is the author and co-editor of three books, all related to electronic packaging. He is the co-founder and founder, respectively, of two spin-off companies, Jacket Micro Devices and E-System Design.

As a member of the program, Boeing will connect to the faculty expertise and highly trained students and graduates of the center as well as an international network of partners in the field of organic photonics and electronics. This includes information on the latest research and discoveries and invitations to exclusive events.

“We’ve joined this center to have access to the state of the art conductive and electro-active technology base that has been assembled at Georgia Tech,” said Patrick Kinlen of Boeing Research & Technology Materials, Processes & Structures Technologies. “This technology has impact for Boeing in the area of conductive coatings, photovoltaics, electrochromics and energy storage.”

“COPE is extremely pleased to count Boeing among its industrial affiliates,” said Bernard Kippelen, Georgia Tech director of the center. “Having a company with a long tradition of aerospace leadership and innovation like The Boeing Company join our center speaks for the strong potential that COPE’s technological innovations can have in the future of commercial jetliners, and in defense, space and security applications.”     

Boeing is the world’s largest aerospace company and leading manufacturer of commercial jetliners and defense, space and security systems. A top U.S. exporter, the company supports airlines and U.S. and allied government customers in 150 countries. Boeing products and tailored services include commercial and military aircraft, satellites, weapons, electronic and defense systems, launch systems, advanced information and communications systems, and performance-based logistics and training.

Boeing Research & Technology is the advanced, central research and development organization of Boeing. It provides innovative technologies that enable the development of future aerospace solutions while improving the cycle time, cost, quality and performance of current aerospace products and services. 

Bahr is a Ph.D. student in the Georgia Tech School of Electrical and Computer Engineering (ECE). He shares this honor with his three coauthors, fellow ECE Ph.D. students Jimmy Hester and John Kimionis, and ECE Professor Emmanouil M. (Manos) Tentzeris, who serves as the Ph.D. advisor for all three students and is the Ken Byers Professor in Flexible Electronics.

Their poster paper, “Additively Manufactured Flexible & Origami-Reconfigurable RF Sensors,” dealt with using novel wireless communication, sensor, and energy harvesting modules on low-cost substrates like paper, plastics, and fabrics, using in-house developed inkjet- and 3D-printed techniques. These modules could find numerous applications in the areas of defense, quality of life, biomonitoring, food quality monitoring, logistics, and the Internet of Things.

GOMACTech primarily reviews developments in microcircuit applications for government systems. Established in 1968, the conference has focused on advances in systems developed by the U.S. Department of Defense and other government agencies. It is also used to announce major government microelectronics initiatives and provides a forum for government reviews.