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  <title><![CDATA[Tom Conte]]></title>
  <body><![CDATA[<p>Tom Conte holds a joint appointment in the schools of Electrical &amp; Computer Engineering and the School of Computer Science at the Georgia Institute of Technology. He received his bachelor’s in electrical engineering from the University of Delaware and received his master’s and doctoral degrees in electrical engineering from the University of Illinois at Ubana-Champaign. Conte's research is in the area of computer architecture, with special emphasis on novel ways to compute. He is widely published and holds 35 patents. Since 2012, he has co-chaired the&nbsp;Institute of Electrical and Electronics Engineers’ (IEEE) “Rebooting Computing” Initiative (rebootingcomputing.ieee.org). In 2015, he served as president of the IEEE Computer Society. Conte is a Fellow of the IEEE and is the past editor in chief of ACM Transactions on Architecture and Compiler Optimization, and the Journal of Instruction-Level Parallelism. He currently directs a group of graduate students studying novel computer architectures (tinker.cc.gatech.edu).&nbsp;</p>]]></body>
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        <value><![CDATA[Center for Research into Novel Computing Hierarchies]]></value>
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        <value><![CDATA[School of Computer Science]]></value>
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        <value><![CDATA[School of Electrical and Computer Engineering]]></value>
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      <value><![CDATA[<ul><li>Computer Architecture</li><li>High-Performance Computing</li></ul>]]></value>
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      <value><![CDATA[<ul><li>9,208,093&nbsp; Allocation of memory space to individual processor cores&nbsp;</li><li>9,189,448&nbsp; Routing image data across on-chip networks&nbsp;</li><li>9,189,282&nbsp; Thread-to-core mapping based on thread deadline, thread demand, and hardware characteristics data collected by a performance counter&nbsp;</li><li>9,178,694&nbsp; Securing backing storage data passed through a network&nbsp;</li><li>8,994,857&nbsp; Camera flash mitigation&nbsp;</li><li>8,924,743&nbsp; Securing data caches through encryption&nbsp;</li><li>8,882,677&nbsp; Microphone for remote health sensing&nbsp;</li><li>8,881,157&nbsp; Allocating threads to cores based on threads falling behind thread completion target deadline&nbsp;</li><li>8,874,855&nbsp; Directory-based coherence caching&nbsp;</li><li>8,866,621&nbsp; Sudden infant death prevention clothing&nbsp;</li><li>8,861,649&nbsp; Power reduction in physical layer wireless communications&nbsp;</li><li>8,854,379&nbsp; Routing across multicore networks using real world or modeled data&nbsp; 8,838,797&nbsp; Dynamic computation allocation&nbsp;</li><li>8,836,516&nbsp; Snoring treatment&nbsp;</li><li>8,830,912&nbsp; Robust multipath routing&nbsp;</li><li>8,824,666&nbsp; Noise cancellation for phone conversation&nbsp;</li><li>8,799,671&nbsp; Techniques for detecting encrypted data&nbsp;</li><li>8,751,854&nbsp; Processor core clock rate selection&nbsp;</li><li>8,726,043&nbsp; Securing backing storage data passed through a network&nbsp;</li><li>8,628,478&nbsp; Microphone for remote health sensing&nbsp;</li><li>8,582,502&nbsp; Robust multipath routing &nbsp;</li><li>8,547,457&nbsp; Camera flash mitigation&nbsp;</li><li>8,508,498&nbsp; Direction and force sensing input device&nbsp;</li><li>8,398,451&nbsp; Tactile input interaction&nbsp;</li><li>8,355,541&nbsp; Texture sensing&nbsp;</li><li>8,352,679&nbsp; Selectively securing data and/or erasing secure data caches responsive to security compromising conditions&nbsp;</li><li>8,244,982&nbsp; Allocating processor cores with cache memory associativity&nbsp;</li><li>8,243,045&nbsp; Touch-sensitive display device and method&nbsp;</li><li>8,203,541&nbsp; OLED display and sensor&nbsp;</li><li>8,193,941&nbsp; Snoring treatment&nbsp;</li><li>8,180,963&nbsp; Hierarchical read-combining local memories&nbsp;</li><li>8,131,970&nbsp; Compiler based cache allocation&nbsp;</li><li>7,953,955&nbsp; Methods and apparatus for automated generation of abbreviated instruction set and configurable processor architecture&nbsp;</li><li>7,865,692&nbsp; Methods and apparatus for automated generation of abbreviated instruction set and configurable processor architecture</li><li>7,028,286&nbsp; Methods and apparatus for automated generation of abbreviated instruction set and configurable processor architecture&nbsp;</li></ul>]]></value>
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      <value><![CDATA[Conte]]></value>
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          <item><![CDATA[CoC Experts Guide Group]]></item>
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