{"558041":{"#nid":"558041","#data":{"type":"news","title":"Georgia Tech to Co-lead NSF Center for Advanced Electronics Through Machine Learning with UIUC and NCSU","body":[{"value":"\u003Cp\u003EThe University of Illinois at Urbana-Champaign has been chosen to lead a new center that aims to speed up the design and verification of microelectronic circuits and systems, reducing development cost and time-to-market for manufacturers of microelectronic products, especially integrated circuits. The Center, co-led by researchers from Georgia Tech and North Carolina State University, is funded for five years through the National Science Foundation\u2019s Industry\/University Cooperative Research Centers (I\/UCRC) program.\u003Cbr \/\u003E \u0026nbsp;\u003Cbr \/\u003E Integrated circuits, or chips, power everything from smart watches to supercomputers. The semiconductor industry \u2013 perennially one of America\u2019s top exporters - has begun searching for new ways to increase performance while reducing chip size and development cost.\u003Cbr \/\u003E \u0026nbsp;\u003Cbr \/\u003E The Center for Advanced Electronics through Machine Learning (CAEML) seeks to accelerate advances by leveraging machine-learning techniques to develop new models for electronic design automation (EDA) tools, which semiconductor companies use to create and verify chip designs for mass-production.\u003Cbr \/\u003E \u0026nbsp;\u003Cbr \/\u003E \u201cWhen products fail qualification testing, it is usually attributed to shortcomings in the models employed by the EDA tools,\u201d said Elyse Rosenbaum, principal investigator and a professor of electrical and computer engineering at Illinois. \u201cMany products have to go through at least one re-spin before entering the marketplace, resulting in the loss of money and time.\u201d\u003Cbr \/\u003E \u0026nbsp;\u003Cbr \/\u003E Currently, chip manufacturers struggle to optimize power, performance, reliability, and cost in their designs, because the analysis is too computationally intensive to execute in a timely manner. CAEML researchers aim to overcome current limitations by employing behavioral models, which look at the behavior, or output, of a chip instead of the internal processes described by physical models most commonly used in today\u2019s designs.\u003Cbr \/\u003E \u0026nbsp;\u003Cbr \/\u003E The CAEML team will create a systematic method for generating behavioral models, which the industry has had only limited success with in the past. The work will draw on deep networks, associative memories, and other research areas within the field of machine learning.\u003Cbr \/\u003E \u0026nbsp;\u003Cbr \/\u003E Researchers will take a comprehensive approach, developing a methodology that is applicable to large systems, with the understanding that most microelectronic systems are comprised of more than just a single chip. Even a \u201csystem on a chip\u201d consists of a package as well as the semiconductor chip, and the system performance is highly affected by the interactions between the two, according to Madhavan Swaminathan, a professor and CAEML site director at Georgia Tech.\u003Cbr \/\u003E \u0026nbsp;\u003Cbr \/\u003E \u201cWith the interface between the chip and the package disappearing through integration, e.g. System in Package technologies, systems need to designed, modeled, and optimized holistically,\u201d said Swaminathan. \u201cOur goal in CAEML is to address systems in such a way that intellectual property can be protected and re-spins minimized.\u201d\u003C\/p\u003E\u003Cp\u003EAs an I\/UCRC, CAEML will collaborate closely with companies, who will help evaluate and select projects. The corporate connections will help researchers better understand the real-world problems faced by manufacturers and provide a pipeline of ideas between academia and industry. They also will help fund the center\u2019s work; currently, 11 companies have committed a total of $550,000 for the first year. NSF will contribute an additional $450,000 per year.\u003Cbr \/\u003E \u0026nbsp;\u003Cbr \/\u003E The collective goal is to create a system to make the design evaluation process much easier, says Paul Franzon, a professor of electrical engineering and CAEML site lead at NC State.\u003Cbr \/\u003E \u0026nbsp;\u003Cbr \/\u003E \u201cI like to say that a silicon chip is the most complex artifact made by man,\u201d Franzon said. \u201cThere are billions of components in a chip-- it is mind-boggling. We\u2019re creating models that help deal with these complexities, so that when we design chips, we design them to work the first time.\u201d\u003Cbr \/\u003E \u0026nbsp;\u003C\/p\u003E\u003Cp align=\u0022center\u0022\u003E\u003Ca href=\u0022https:\/\/publish.illinois.edu\/advancedelectronics\/\u0022 target=\u0022_blank\u0022\u003E\u003Cstrong\u003EVisit the CAEML Program Website Here\u003C\/strong\u003E\u003C\/a\u003E \u003C\/p\u003E\u003Cp align=\u0022center\u0022\u003EFor more information, contact Dr. Madhavan Swaminathan (\u003Ca href=\u0022mailto:madhavan.swaminathan@ece.gatech.edu\u0022\u003Emadhavan.swaminathan@ece.gatech.edu\u003C\/a\u003E)\u003C\/p\u003E","summary":null,"format":"limited_html"}],"field_subtitle":"","field_summary":"","field_summary_sentence":[{"value":"The Center for Advanced Electronics through Machine Learning (CAEML) seeks to accelerate advances by leveraging machine-learning techniques to develop new models for electronic design automation (EDA) tools create and verify chip designs for market."}],"uid":"27863","created_gmt":"2016-08-02 14:22:40","changed_gmt":"2016-10-08 03:22:12","author":"Christa Ernst","boilerplate_text":"","field_publication":"","field_article_url":"","dateline":{"date":"2016-08-02T00:00:00-04:00","iso_date":"2016-08-02T00:00:00-04:00","tz":"America\/New_York"},"extras":[],"hg_media":{"558021":{"id":"558021","type":"image","title":"Madhavan Swaminathan","body":null,"created":"1470161828","gmt_created":"2016-08-02 18:17:08","changed":"1475895361","gmt_changed":"2016-10-08 02:56:01","alt":"Madhavan Swaminathan","file":{"fid":"206714","name":"madhavanswaminathan_official_inst_photo.png","image_path":"\/sites\/default\/files\/images\/madhavanswaminathan_official_inst_photo.png","image_full_path":"http:\/\/www.tlwarc.hg.gatech.edu\/\/sites\/default\/files\/images\/madhavanswaminathan_official_inst_photo.png","mime":"image\/png","size":267955,"path_740":"http:\/\/www.tlwarc.hg.gatech.edu\/sites\/default\/files\/styles\/740xx_scale\/public\/images\/madhavanswaminathan_official_inst_photo.png?itok=Z4KZ1FXL"}}},"media_ids":["558021"],"groups":[{"id":"197261","name":"Institute for Electronics and Nanotechnology"}],"categories":[{"id":"129","name":"Institute and Campus"},{"id":"132","name":"Institute Leadership"},{"id":"153","name":"Computer Science\/Information Technology and Security"},{"id":"145","name":"Engineering"},{"id":"149","name":"Nanotechnology and Nanoscience"}],"keywords":[{"id":"39591","name":"computational modeling"},{"id":"94171","name":"Electronics Packaging"},{"id":"9167","name":"machine learning"},{"id":"24251","name":"Madhavan Swaminathan"},{"id":"167954","name":"semiconductor fabrication"},{"id":"166968","name":"the Institute for Electronics and Nanotechnology"},{"id":"168380","name":"the School of Electrical and Computer Engineering"}],"core_research_areas":[{"id":"39451","name":"Electronics and Nanotechnology"}],"news_room_topics":[],"event_categories":[],"invited_audience":[],"affiliations":[],"classification":[],"areas_of_expertise":[],"news_and_recent_appearances":[],"phone":[],"contact":[],"email":["madhavan.swaminathan@ece.gatech.edu"],"slides":[],"orientation":[],"userdata":""}}}