{"61435":{"#nid":"61435","#data":{"type":"news","title":"New Graphene Fabrication Method Uses Silicon Carbide Template","body":[{"value":"\u003Cp\u003EResearchers at the Georgia Institute of Technology have developed a new \u201ctemplated growth\u201d technique for fabricating nanometer-scale graphene devices.  The method addresses what had been a significant obstacle to the use of this promising material in future generations of high-performance electronic devices.\u003C\/p\u003E\n\u003Cp\u003EThe technique involves etching patterns into the silicon carbide surfaces on which epitaxial graphene is grown.  The patterns serve as templates directing the growth of graphene structures, allowing the formation of nanoribbons of specific widths without the use of e-beams or other destructive cutting techniques.  Graphene nanoribbons produced with these templates have smooth edges that avoid electron-scattering problems.\n\u003C\/p\u003E\n\u003Cp\u003E\u0022Using this approach, we can make very narrow ribbons of interconnected graphene without the rough edges,\u0022 said Walt de Heer, a professor in the Georgia Tech School of Physics.  \u0022Anything that can be done to make small structures without having to cut them is going to be useful to the development of graphene electronics because if the edges are too rough, electrons passing through the ribbons scatter against the edges and reduce the desirable properties of graphene.\u0022\n\u003C\/p\u003E\n\u003Cp\u003EThe new technique has been used to fabricate an array of 10,000 top-gated graphene transistors on a 0.24 square centimeter chip \u2013 believed to be the largest density of graphene devices reported so far.\n\u003C\/p\u003E\n\u003Cp\u003EThe research was reported Oct. 3 in the advance online edition of the journal \u003Cem\u003ENature Nanotechnology\u003C\/em\u003E.  The work was supported by the National Science Foundation, the W.M. Keck Foundation and the Nanoelectronics Research Initiative Institute for Nanoelectronics Discovery and Exploration (INDEX).\n\u003C\/p\u003E\n\u003Cp\u003EIn creating their graphene nanostructures, De Heer and his research team first use conventional microelectronics techniques to etch tiny \u0022steps\u0022 \u2013 or contours \u2013 into a silicon carbide wafer.  They then heat the contoured wafer to approximately 1,500 degrees Celsius, which initiates melting that polishes any rough edges left by the etching process.\n\u003C\/p\u003E\n\u003Cp\u003EThey then use established techniques for growing graphene from silicon carbide by driving off the silicon atoms from the surface.  Instead of producing a consistent layer of graphene one atom thick across the surface of the wafer, however, the researchers limit the heating time so that graphene grows only on the edges of the contours.\n\u003C\/p\u003E\n\u003Cp\u003ETo do this, they take advantage of the fact that graphene grows more rapidly on certain facets of the silicon carbide crystal than on others.  The width of the resulting nanoribbons is proportional to the depth of the contour, providing a mechanism for precisely controlling the nanoribbons.  To form complex graphene structures, multiple etching steps can be carried out to create a complex template, de Heer explained.\n\u003C\/p\u003E\n\u003Cp\u003E\u0022By using the silicon carbide to provide the template, we can grow graphene in exactly the sizes and shapes that we want,\u0022 he said. \u0022Cutting steps of various depths allows us to create graphene structures that are interconnected in the way we want them to be.\u0022\n\u003C\/p\u003E\n\u003Cp\u003EIn nanometer-scale graphene ribbons, quantum confinement makes the material behave as a semiconductor suitable for creation of electronic devices.  But in ribbons a micron or more wide, the material acts as a conductor.  Controlling the depth of the silicon carbide template allows the researchers to create these different structures simultaneously, using the same growth process.  \n\u003C\/p\u003E\n\u003Cp\u003E\u0022The same material can be either a conductor or a semiconductor depending on its shape,\u0022 noted de Heer, who is also a faculty member in Georgia Tech\u2019s National Science Foundation-supported Materials Research Science and Engineering Center (MRSEC).  \u0022One of the major advantages of graphene electronics is to make the device leads and the semiconducting ribbons from the same material.  That\u0027s important to avoid electrical resistance that builds up at junctions between different materials.\u0022\n\u003C\/p\u003E\n\u003Cp\u003EAfter formation of the nanoribbons \u2013 which can be as narrow as 40 nanometers \u2013 the researchers apply a dielectric material and metal gate to construct field-effect transistors.  While successful fabrication of high-quality transistors demonstrates graphene\u0027s viability as an electronic material, de Heer sees them as only the first step in what could be done with the material.\n\u003C\/p\u003E\n\u003Cp\u003E\u0022When we manage to make devices well on the nanoscale, we can then move on to make much smaller and finer structures that will go beyond conventional transistors to open up the possibility for more sophisticated devices that use electrons more like light than particles,\u0022 he said.  \u0022If we can factor quantum mechanical features into electronics, that is going to open up a lot of new possibilities.\u0022\n\u003C\/p\u003E\n\u003Cp\u003EDe Heer and his research team are now working to create smaller structures, and to integrate the graphene devices with silicon.  The researchers are also working to improve the field-effect transistors with thinner dielectric materials.\n\u003C\/p\u003E\n\u003Cp\u003EUltimately, graphene may be the basis for a generation of high-performance devices that will take advantage of the material\u0027s unique properties in applications where the higher cost can be justified.  Silicon will continue to be used in applications that don\u0027t require such high performance, de Heer said.\n\u003C\/p\u003E\n\u003Cp\u003E\u0022This is another step showing that our method of working with epitaxial graphene on silicon carbide is the right approach and the one that will probably be used for making graphene electronics,\u0022 he added.  \u0022This is a significant new step toward electronics manufacturing with graphene.\u0022\n\u003C\/p\u003E\n\u003Cp\u003EIn addition to those already mentioned, the research has involved M. Sprinkle, M. Ruan, Y Hu, J. Hankinson, M. Rubio-Roy, B. Zhang, X. Wu and C. Berger.\n\u003C\/p\u003E\n\u003Cp\u003E\u003Cstrong\u003EResearch News \u0026amp; Publications Office\u003Cbr \/\u003E\nGeorgia Institute of Technology\u003Cbr \/\u003E\n75 Fifth Street, N.W., Suite 314\u003Cbr \/\u003E\nAtlanta, Georgia  30308  USA\u003C\/strong\u003E\n\u003C\/p\u003E\n\u003Cp\u003E\u003Cstrong\u003EMedia Relations Contacts\u003C\/strong\u003E: John Toon (404-894-6986)(\u003Ca href=\u0022mailto:jtoon@gatech.edu\u0022\u003Ejtoon@gatech.edu\u003C\/a\u003E) or Abby Vogel Robinson (404-385-3364)(\u003Ca href=\u0022mailto:abby@innovate.gatech.edu\u0022\u003Eabby@innovate.gatech.edu\u003C\/a\u003E).\n\u003C\/p\u003E\n\u003Cp\u003E\u003Cstrong\u003EWriter\u003C\/strong\u003E: John Toon\n\u003C\/p\u003E\n\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E","summary":null,"format":"limited_html"}],"field_subtitle":"","field_summary":[{"value":"\u003Cp\u003EGeorgia Tech researchers have developed a new \u0022templated growth\u0022 technique for fabricating nanometer-scale graphene devices.  The method addresses what had been a significant obstacle to the use of this promising material in future generations of high-performance electronic devices.\u003C\/p\u003E","format":"limited_html"}],"field_summary_sentence":[{"value":"A new template approach is being used to fabricate graphene devi"}],"uid":"27303","created_gmt":"2010-10-05 00:00:00","changed_gmt":"2016-10-08 03:07:34","author":"John Toon","boilerplate_text":"","field_publication":"","field_article_url":"","dateline":{"date":"2010-10-05T00:00:00-04:00","iso_date":"2010-10-05T00:00:00-04:00","tz":"America\/New_York"},"extras":[],"hg_media":{"61436":{"id":"61436","type":"image","title":"Graphene transistors","body":null,"created":"1449176337","gmt_created":"2015-12-03 20:58:57","changed":"1475894536","gmt_changed":"2016-10-08 02:42:16","alt":"Graphene transistors","file":{"fid":"191358","name":"tcv90049.jpg","image_path":"\/sites\/default\/files\/images\/tcv90049_0.jpg","image_full_path":"http:\/\/www.tlwarc.hg.gatech.edu\/\/sites\/default\/files\/images\/tcv90049_0.jpg","mime":"image\/jpeg","size":535060,"path_740":"http:\/\/www.tlwarc.hg.gatech.edu\/sites\/default\/files\/styles\/740xx_scale\/public\/images\/tcv90049_0.jpg?itok=IZZUcHgA"}},"61437":{"id":"61437","type":"image","title":"Graphene nanoribbon","body":null,"created":"1449176337","gmt_created":"2015-12-03 20:58:57","changed":"1475894536","gmt_changed":"2016-10-08 02:42:16","alt":"Graphene nanoribbon","file":{"fid":"191359","name":"trf90049.jpg","image_path":"\/sites\/default\/files\/images\/trf90049_0.jpg","image_full_path":"http:\/\/www.tlwarc.hg.gatech.edu\/\/sites\/default\/files\/images\/trf90049_0.jpg","mime":"image\/jpeg","size":609209,"path_740":"http:\/\/www.tlwarc.hg.gatech.edu\/sites\/default\/files\/styles\/740xx_scale\/public\/images\/trf90049_0.jpg?itok=I30e2Uoy"}}},"media_ids":["61436","61437"],"related_links":[{"url":"http:\/\/www.physics.gatech.edu\/","title":"Georgia Tech School of Physics"},{"url":"http:\/\/www.physics.gatech.edu\/people\/faculty\/wdeheer.html","title":"Walt de Heer"},{"url":"http:\/\/mrsec.gatech.edu\/","title":"Materials Research Science and Engineering Center (MRSEC)"}],"groups":[{"id":"1188","name":"Research Horizons"}],"categories":[{"id":"141","name":"Chemistry and Chemical Engineering"},{"id":"145","name":"Engineering"},{"id":"149","name":"Nanotechnology and Nanoscience"},{"id":"135","name":"Research"},{"id":"150","name":"Physics and Physical Sciences"}],"keywords":[{"id":"1928","name":"devices"},{"id":"4264","name":"fabrication"},{"id":"429","name":"graphene"},{"id":"10851","name":"template"},{"id":"7528","name":"transistors"}],"core_research_areas":[],"news_room_topics":[],"event_categories":[],"invited_audience":[],"affiliations":[],"classification":[],"areas_of_expertise":[],"news_and_recent_appearances":[],"phone":[],"contact":[{"value":"\u003Cp\u003E\u003Cstrong\u003EJohn Toon\u003C\/strong\u003E\u003Cbr \/\u003EResearch News \u0026amp; Publications Office\u003Cbr \/\u003E\u003Ca href=\u0022http:\/\/www.gatech.edu\/contact\/index.html?id=jt7\u0022\u003EContact John Toon\u003C\/a\u003E\u003Cbr \/\u003E\u003Cstrong\u003E404-894-6986\u003C\/strong\u003E\u003C\/p\u003E","format":"limited_html"}],"email":["jtoon@gatech.edu"],"slides":[],"orientation":[],"userdata":""}}}