{"62553":{"#nid":"62553","#data":{"type":"event","title":"MSE M.S. Defense \u2013 Abhishek Choudhury","body":[{"value":"\u003Cp\u003E\u003Cstrong\u003EThesis Title:\u003C\/strong\u003E Chip-Last Embedded Low Temperature\nInterconnections With Chip-First Dimensions\u003C\/p\u003E\u003Cp\u003E\u0026nbsp;\u003C\/p\u003E\n\n\n\n\u003Cp\u003E\u003Cstrong\u003EAbstract:\u003C\/strong\u003E\u003C\/p\u003E\n\n\n\n\u003Cp\u003ESmall form-factor packages with high integration density are\ndriving the innovations in chip-to-package interconnections. Metallurgical\ninterconnections have evolved from the conventional eutectic and lead-free\nsolders to fine pitch copper pillars with lead-free solder cap. However,\nscaling down the bump pitch below 50-80\u00b5m and increasing the interconnect\ndensity with this approach creates a challenge in terms of accurate solder mask\nlithography and joint reliability with low stand-off heights. Going beyond the\nstate of the art flip-chip interconnection technology to achieve ultra-fine\nbump pitch and high reliability requires a fundamentally- different approach\ntowards highly functional and integrated systems. This research demonstrates a\nlow-profile copper-to-copper interconnect material and process approach with\nless than 20\u00b5m total height using adhesive bonding at lower temperature than\nother state-of-the-art methods. The research focuses on: (1) exploring a novel\nsolution for ultra-fine pitch (\u0026lt; 30\u00b5m) interconnections, (2) advanced\nmaterials and assembly process for copper-to-copper interconnections, and (3)\ndesign, fabrication and characterization of test vehicles for reliability and\nfailure analysis of the interconnection. \u003C\/p\u003E\n\n\u003Cp\u003EThis research represents the first demonstration of\nultra-fine pitch Cu-to-Cu interconnection below 200\u00b0C using non-conductive film\n(NCF) as an adhesive to achieve bonding between silicon die and organic\nsubstrate. The fabrication process optimization and characterization of copper\nbumps, NCF and build-up substrate was performed as a part of the study. The\ntest vehicles were studied for mechanical reliability performance under\nunbiased highly accelerated stress test (U-HAST), high temperature storage\n(HTS) and thermal shock test (TST). This robust interconnect scheme was also\nshown to perform well with different die sizes, die thicknesses and with\nembedded dies. A simple and reliable, low-cost and low-temperature direct Cu-Cu\nbonding was demonstrated offering a potential solution for future flip chip\npackages as well as with chip-last embedded active devices in organic\nsubstrates.\u003C\/p\u003E","summary":null,"format":"limited_html"}],"field_subtitle":"","field_summary":[{"value":"\u003Cp\u003EThesis Title: Chip-Last Embedded Low Temperature\nInterconnections With Chip-First Dimensions\u003C\/p\u003E\u003Cp\u003ETime: 1:30 PM, Tuesday 8th November\u003C\/p\u003E\n\n\u003Cp\u003ELocation: MaRC 351\u003C\/p\u003E","format":"limited_html"}],"field_summary_sentence":[{"value":"MSE M.S. Defense \u2013 Abhishek Choudhury"}],"uid":"27388","created_gmt":"2010-11-05 10:52:36","changed_gmt":"2016-10-08 01:53:24","author":"Bill Miller","boilerplate_text":"","field_publication":"","field_article_url":"","field_event_time":{"event_time_start":"2010-11-08T00:30:00-05:00","event_time_end":"2010-11-08T02:30:00-05:00","event_time_end_last":"2010-11-08T02:30:00-05:00","gmt_time_start":"2010-11-08 05:30:00","gmt_time_end":"2010-11-08 07:30:00","gmt_time_end_last":"2010-11-08 07:30:00","rrule":null,"timezone":"America\/New_York"},"extras":[],"groups":[{"id":"1238","name":"School of Materials Science and Engineering"}],"categories":[],"keywords":[{"id":"10802","name":"MSE_Interal_Event"}],"core_research_areas":[],"news_room_topics":[],"event_categories":[],"invited_audience":[],"affiliations":[],"classification":[],"areas_of_expertise":[],"news_and_recent_appearances":[],"phone":[],"contact":[],"email":[],"slides":[],"orientation":[],"userdata":""}}}