672247 event 1705531848 1705531862 <![CDATA[Ph.D. Proposal Oral Exam - Neslon Sepulveda]]> Title:  Back-end-of-line Potential as a Performance Enhancement Technique for Next-Generation SiGe HBT’s BICMOS Devices

Committee: 

Dr. Cressler, Advisor     

Dr. Ansari, Chair

Dr. Ghalichechian

]]> The objective of the proposed research is to explore the potential of the back-end-of-line (BEOL) as a performance enhancement technique to design next-generation SiGe BiCMOS devices. Modern SiGe BiCMOS technology has significant potential for high-speed, high-power applications in the sub-THz range, where improvements are made continuously with the help of advanced fabrication techniques and an improved understanding of underlying reliability physics. To achieve this potential, I propose to study the RF Breakdown due to the BEOL. Following a recent unique phenomenon to achieve improved device performance using mechanical stress from the back-end-of-the-line (BEOL) has been identified. Preliminary research showed DC reliability results due to BEOL being considered a performance enhancement technique. Following DC reliability results, for robust circuit design is critical to study how the RF breakdown will change due to the BEOL. This RF domain characterization will aid in the implementation of next-generation circuit designs with improved performance and reliability. Next is to understand the impact of BEOL over a wide range of temperatures which is another unexplored area. I propose to study the reliability impact of BEOL dummy metal layers as a performance enhancement technique in operation over a wide range of temperatures and its related physics. To understand this behavior for circuit design considerations, experimentation must be performed on SiGe at cryogenic and elevated temperatures. Further, potential cryogenic reliability issues arise, such as the impact of the back-end-of-the-line layout on the device performance, and device-to-device variability.

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